Simulation Results: spi_device/2p

 
07/04/2026 19:25:09 DVSim: v1.17.3 sha: f66d746 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.62 %
  • code
  • 93.65 %
  • assert
  • 94.62 %
  • func
  • 71.58 %
  • line
  • 99.09 %
  • branch
  • 98.33 %
  • cond
  • 95.87 %
  • toggle
  • 87.74 %
  • FSM
  • 87.23 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 98.840s 49202.710us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 0.990s 40.819us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 2.120s 341.804us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 16.410s 2289.711us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 10.690s 419.323us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 1.830s 24.433us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 2.120s 341.804us 1 1 100.00
spi_device_csr_aliasing 10.690s 419.323us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.740s 11.027us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.260s 58.259us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.860s 64.895us 1 1 100.00
mem_parity 1 1 100.00
spi_device_mem_parity 0.970s 23.625us 1 1 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 0.870s 20.947us 1 1 100.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.070s 43.245us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.070s 43.245us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 2.910s 10981.203us 1 1 100.00
spi_device_tpm_sts_read 0.880s 184.468us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 14.830s 2574.108us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 2.780s 3134.080us 1 1 100.00
spi_device_flash_all 242.830s 263436.423us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 16.230s 31726.160us 1 1 100.00
spi_device_flash_all 242.830s 263436.423us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 16.230s 31726.160us 1 1 100.00
spi_device_flash_all 242.830s 263436.423us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 242.830s 263436.423us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 5.640s 973.992us 1 1 100.00
spi_device_flash_all 242.830s 263436.423us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 5.640s 973.992us 1 1 100.00
spi_device_flash_all 242.830s 263436.423us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 5.640s 973.992us 1 1 100.00
spi_device_flash_all 242.830s 263436.423us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 5.640s 973.992us 1 1 100.00
spi_device_flash_all 242.830s 263436.423us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 5.640s 973.992us 1 1 100.00
spi_device_flash_all 242.830s 263436.423us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 6.120s 488.877us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 7.290s 2358.522us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 7.290s 2358.522us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 7.290s 2358.522us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 6.240s 1020.936us 1 1 100.00
spi_device_read_buffer_direct 2.530s 388.627us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 7.290s 2358.522us 1 1 100.00
spi_device_flash_all 242.830s 263436.423us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 242.830s 263436.423us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 242.830s 263436.423us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 2.260s 488.611us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 2.260s 488.611us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 98.840s 49202.710us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 290.510s 273493.204us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 17.000s 3185.053us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.660s 15.052us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.880s 33.074us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 3.480s 800.436us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 3.480s 800.436us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 0.990s 40.819us 1 1 100.00
spi_device_csr_rw 2.120s 341.804us 1 1 100.00
spi_device_csr_aliasing 10.690s 419.323us 1 1 100.00
spi_device_same_csr_outstanding 1.460s 26.356us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 0.990s 40.819us 1 1 100.00
spi_device_csr_rw 2.120s 341.804us 1 1 100.00
spi_device_csr_aliasing 10.690s 419.323us 1 1 100.00
spi_device_same_csr_outstanding 1.460s 26.356us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_tl_intg_err 15.540s 837.504us 1 1 100.00
spi_device_sec_cm 1.150s 55.503us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 15.540s 837.504us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 108.350s 113291.474us 1 1 100.00