Simulation Results: sram_ctrl/main

 
07/04/2026 19:25:09 DVSim: v1.17.3 sha: f66d746 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.04 %
  • code
  • 93.46 %
  • assert
  • 95.92 %
  • func
  • 95.73 %
  • line
  • 98.74 %
  • branch
  • 96.97 %
  • cond
  • 91.72 %
  • toggle
  • 89.38 %
  • FSM
  • 90.48 %
Validation stages
V1
100.00%
V2
100.00%
V2S
90.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 20.780s 2932.899us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.870s 96.338us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.660s 25.000us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.730s 163.408us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.770s 80.319us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.690s 359.034us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.660s 25.000us 1 1 100.00
sram_ctrl_csr_aliasing 0.770s 80.319us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 244.800s 65810.862us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 120.840s 10465.411us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 111.690s 4198.986us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 235.340s 19822.643us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 493.570s 55813.445us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 253.440s 46902.259us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 45.480s 37724.143us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 1073.210s 56664.798us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 54.200s 2704.779us 1 1 100.00
sram_ctrl_partial_access_b2b 261.740s 54042.056us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 4.990s 801.672us 1 1 100.00
sram_ctrl_throughput_w_partial_write 16.590s 2910.418us 1 1 100.00
sram_ctrl_throughput_w_readback 4.820s 1166.501us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 404.170s 17904.189us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.280s 358.631us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 4348.600s 1546351.211us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.760s 17.762us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.950s 111.559us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.950s 111.559us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.870s 96.338us 1 1 100.00
sram_ctrl_csr_rw 0.660s 25.000us 1 1 100.00
sram_ctrl_csr_aliasing 0.770s 80.319us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.930s 66.190us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.870s 96.338us 1 1 100.00
sram_ctrl_csr_rw 0.660s 25.000us 1 1 100.00
sram_ctrl_csr_aliasing 0.770s 80.319us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.930s 66.190us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 29.040s 7459.673us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_sec_cm 0.660s 18.494us 0 1 0.00
sram_ctrl_tl_intg_err 2.130s 197.183us 1 1 100.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.660s 18.494us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.130s 197.183us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 404.170s 17904.189us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 404.170s 17904.189us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.660s 25.000us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 1073.210s 56664.798us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 1073.210s 56664.798us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 1073.210s 56664.798us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 45.480s 37724.143us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 3.740s 2664.672us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 29.040s 7459.673us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 3.920s 704.481us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 20.780s 2932.899us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 20.780s 2932.899us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 1073.210s 56664.798us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.660s 18.494us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 45.480s 37724.143us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.660s 18.494us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.660s 18.494us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 20.780s 2932.899us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.660s 18.494us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 7.670s 4169.431us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 64547859466400601197613679465695813618486027772550322135180050303886003272931 100
UVM_ERROR @ 18493886 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 18493886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---