Simulation Results: sram_ctrl/ret

 
07/04/2026 19:25:09 DVSim: v1.17.3 sha: f66d746 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.76 %
  • code
  • 95.57 %
  • assert
  • 95.61 %
  • func
  • 96.10 %
  • line
  • 99.13 %
  • branch
  • 97.86 %
  • cond
  • 91.49 %
  • toggle
  • 89.35 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
90.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 24.020s 918.535us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.900s 45.595us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.710s 34.216us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.200s 119.577us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.840s 27.851us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.240s 34.838us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.710s 34.216us 1 1 100.00
sram_ctrl_csr_aliasing 0.840s 27.851us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 9.790s 691.944us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 3.050s 65.872us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 572.820s 66043.196us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 262.210s 3515.264us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 13.530s 900.500us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 372.060s 2951.748us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 3.810s 3879.088us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 428.460s 26259.535us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 10.430s 1366.335us 1 1 100.00
sram_ctrl_partial_access_b2b 252.770s 48883.398us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 10.340s 109.802us 1 1 100.00
sram_ctrl_throughput_w_partial_write 64.660s 315.060us 1 1 100.00
sram_ctrl_throughput_w_readback 36.090s 945.212us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 614.160s 13393.133us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 0.970s 28.891us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 3083.000s 223847.138us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.750s 106.393us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.270s 90.963us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.270s 90.963us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.900s 45.595us 1 1 100.00
sram_ctrl_csr_rw 0.710s 34.216us 1 1 100.00
sram_ctrl_csr_aliasing 0.840s 27.851us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.980s 32.651us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.900s 45.595us 1 1 100.00
sram_ctrl_csr_rw 0.710s 34.216us 1 1 100.00
sram_ctrl_csr_aliasing 0.840s 27.851us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.980s 32.651us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.680s 1760.641us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_tl_intg_err 2.280s 268.398us 1 1 100.00
sram_ctrl_sec_cm 0.840s 3.605us 0 1 0.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.840s 3.605us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.280s 268.398us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 614.160s 13393.133us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 614.160s 13393.133us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.710s 34.216us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 428.460s 26259.535us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 428.460s 26259.535us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 428.460s 26259.535us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 3.810s 3879.088us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 0.920s 36.419us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.680s 1760.641us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 1.260s 128.416us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 24.020s 918.535us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 24.020s 918.535us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 428.460s 26259.535us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.840s 3.605us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 3.810s 3879.088us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.840s 3.605us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.840s 3.605us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 24.020s 918.535us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.840s 3.605us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 7.370s 1421.930us 1 1 100.00

Error Messages

   Test seed line log context
Offending '(!$isunknown(rdata_o))'
sram_ctrl_sec_cm 38653816281890442968852727536210521790400789615101430560300310541227039782613 99
Offending '(!$isunknown(rdata_o))'
UVM_ERROR @ 3605081 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 3605081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---