Simulation Results: sysrst_ctrl

 
07/04/2026 19:25:09 DVSim: v1.17.3 sha: f66d746 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.61 %
  • code
  • 90.40 %
  • assert
  • 88.79 %
  • func
  • 65.65 %
  • line
  • 95.92 %
  • branch
  • 96.48 %
  • cond
  • 92.93 %
  • toggle
  • 100.00 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 1.250s 2144.111us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 2.230s 2501.084us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 5.130s 2435.211us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 1.920s 2291.096us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 7.780s 4029.243us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 2.810s 2086.927us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 23.270s 45181.072us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 4.450s 3281.279us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 4.810s 2060.582us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 2.810s 2086.927us 1 1 100.00
sysrst_ctrl_csr_aliasing 4.450s 3281.279us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 55.710s 33202.277us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 36.410s 84965.607us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 6.600s 3412.505us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 2.890s 3085.473us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 5.040s 2511.508us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 5.010s 2218.451us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 6.730s 3334.870us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 2.110s 2629.097us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 17.660s 253436.085us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 76.840s 42969.131us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 14.070s 7066.883us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 1.980s 2042.774us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 4.210s 2010.955us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 3.930s 2284.711us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 3.930s 2284.711us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 7.780s 4029.243us 1 1 100.00
sysrst_ctrl_csr_rw 2.810s 2086.927us 1 1 100.00
sysrst_ctrl_csr_aliasing 4.450s 3281.279us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 6.260s 7658.063us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 7.780s 4029.243us 1 1 100.00
sysrst_ctrl_csr_rw 2.810s 2086.927us 1 1 100.00
sysrst_ctrl_csr_aliasing 4.450s 3281.279us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 6.260s 7658.063us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_tl_intg_err 21.540s 42791.087us 1 1 100.00
sysrst_ctrl_sec_cm 79.690s 42009.264us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 21.540s 42791.087us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 6.130s 2836.011us 1 1 100.00