Simulation Results: uart

 
07/04/2026 19:25:09 DVSim: v1.17.3 sha: f66d746 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.58 %
  • code
  • 95.04 %
  • assert
  • 97.12 %
  • func
  • 55.59 %
  • line
  • 98.86 %
  • branch
  • 96.50 %
  • cond
  • 93.47 %
  • toggle
  • 91.32 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.460s 633.639us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.600s 51.896us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.590s 41.128us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.170s 139.520us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.660s 48.779us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.990s 27.738us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.590s 41.128us 1 1 100.00
uart_csr_aliasing 0.660s 48.779us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 39.540s 74361.132us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.460s 633.639us 1 1 100.00
uart_tx_rx 39.540s 74361.132us 1 1 100.00
parity_error 2 2 100.00
uart_intr 8.340s 15318.455us 1 1 100.00
uart_rx_parity_err 6.980s 68580.094us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 39.540s 74361.132us 1 1 100.00
uart_intr 8.340s 15318.455us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 28.560s 104305.056us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 14.970s 56656.684us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 101.520s 99764.782us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 8.340s 15318.455us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 8.340s 15318.455us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 8.340s 15318.455us 1 1 100.00
perf 1 1 100.00
uart_perf 338.160s 16676.171us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 3.880s 3654.470us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 3.880s 3654.470us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 0.900s 975.910us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 1.120s 1898.886us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.710s 1840.091us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 6.690s 3253.209us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 238.560s 123269.819us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 172.420s 184915.171us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.550s 14.764us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.570s 12.173us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.420s 84.910us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.420s 84.910us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.600s 51.896us 1 1 100.00
uart_csr_rw 0.590s 41.128us 1 1 100.00
uart_csr_aliasing 0.660s 48.779us 1 1 100.00
uart_same_csr_outstanding 0.720s 120.635us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.600s 51.896us 1 1 100.00
uart_csr_rw 0.590s 41.128us 1 1 100.00
uart_csr_aliasing 0.660s 48.779us 1 1 100.00
uart_same_csr_outstanding 0.720s 120.635us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_tl_intg_err 0.840s 365.649us 1 1 100.00
uart_sec_cm 0.770s 494.004us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 0.840s 365.649us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
uart_stress_all_with_rand_reset 13.720s 9825.846us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = *
uart_noise_filter 100105627830707365982333240270825735456337308636381585061214882545817080631641 74
UVM_ERROR @ 9527154 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 9527154 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 500531082 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
UVM_ERROR @ 501572757 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
UVM_ERROR @ 505197786 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
uart_stress_all_with_rand_reset 36056745330708096182330994254063578589939347034527347128401986526330060452366 132
UVM_ERROR @ 9319165898 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 9320565898 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 9322205898 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 9324045898 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 9325605898 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0