Simulation Results: adc_ctrl

 
08/04/2026 18:06:49 DVSim: v1.17.3 sha: 007b0cf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 70.28 %
  • code
  • 96.88 %
  • assert
  • 95.62 %
  • func
  • 18.34 %
  • line
  • 99.05 %
  • branch
  • 97.77 %
  • cond
  • 93.01 %
  • toggle
  • 100.00 %
  • FSM
  • 94.59 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 10.170s 5837.694us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.750s 830.560us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 0.780s 583.867us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 41.020s 26702.550us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 2.000s 1252.392us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 0.960s 610.691us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 0.780s 583.867us 1 1 100.00
adc_ctrl_csr_aliasing 2.000s 1252.392us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 1 1 100.00
adc_ctrl_filters_polled 87.010s 160936.091us 1 1 100.00
filters_polled_fixed 1 1 100.00
adc_ctrl_filters_polled_fixed 23.840s 163308.715us 1 1 100.00
filters_interrupt 1 1 100.00
adc_ctrl_filters_interrupt 464.500s 323185.614us 1 1 100.00
filters_interrupt_fixed 1 1 100.00
adc_ctrl_filters_interrupt_fixed 774.060s 495405.732us 1 1 100.00
filters_wakeup 1 1 100.00
adc_ctrl_filters_wakeup 322.630s 397177.217us 1 1 100.00
filters_wakeup_fixed 1 1 100.00
adc_ctrl_filters_wakeup_fixed 135.870s 386803.143us 1 1 100.00
filters_both 1 1 100.00
adc_ctrl_filters_both 844.260s 526698.519us 1 1 100.00
clock_gating 1 1 100.00
adc_ctrl_clock_gating 211.450s 531300.586us 1 1 100.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 7.330s 4736.741us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 47.430s 43609.377us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 80.780s 96788.280us 1 1 100.00
stress_all 1 1 100.00
adc_ctrl_stress_all 24.450s 17921.300us 1 1 100.00
alert_test 1 1 100.00
adc_ctrl_alert_test 0.680s 355.451us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 0.800s 485.540us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 1.780s 533.303us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 1.780s 533.303us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.750s 830.560us 1 1 100.00
adc_ctrl_csr_rw 0.780s 583.867us 1 1 100.00
adc_ctrl_csr_aliasing 2.000s 1252.392us 1 1 100.00
adc_ctrl_same_csr_outstanding 4.270s 4830.485us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.750s 830.560us 1 1 100.00
adc_ctrl_csr_rw 0.780s 583.867us 1 1 100.00
adc_ctrl_csr_aliasing 2.000s 1252.392us 1 1 100.00
adc_ctrl_same_csr_outstanding 4.270s 4830.485us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 3.620s 7945.729us 1 1 100.00
adc_ctrl_tl_intg_err 2.290s 4586.297us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 2.290s 4586.297us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
adc_ctrl_stress_all_with_rand_reset 4.540s 2567.797us 1 1 100.00