Simulation Results: chip

 
08/04/2026 18:06:49 DVSim: v1.17.3 sha: 007b0cf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 76.30 %
  • code
  • 85.09 %
  • assert
  • 97.37 %
  • func
  • 46.44 %
  • line
  • 94.25 %
  • branch
  • 93.63 %
  • cond
  • 89.13 %
  • toggle
  • 91.29 %
  • FSM
  • 57.14 %
Validation stages
V1
100.00%
V2
83.45%
V2S
50.00%
V3
65.38%
unmapped
75.00%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 4 4 100.00
chip_sw_example_flash 169.330s 3252.755us 1 1 100.00
chip_sw_example_rom 54.070s 2309.286us 1 1 100.00
chip_sw_example_manufacturer 142.760s 2450.696us 1 1 100.00
chip_sw_example_concurrency 171.160s 2907.391us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 148.900s 5231.599us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 320.240s 5634.833us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 387.400s 6878.282us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 3456.510s 27978.691us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
chip_csr_mem_rw_with_rand_reset 279.560s 6057.300us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 3456.510s 27978.691us 1 1 100.00
chip_csr_rw 320.240s 5634.833us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 6.370s 201.030us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 305.150s 4006.142us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 305.150s 4006.142us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 305.150s 4006.142us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 339.610s 3520.866us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 339.610s 3520.866us 1 1 100.00
chip_sw_uart_tx_rx_idx1 378.220s 4672.202us 1 1 100.00
chip_sw_uart_tx_rx_idx2 408.810s 4197.626us 1 1 100.00
chip_sw_uart_tx_rx_idx3 381.180s 4502.461us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 335.390s 4173.866us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 974.450s 8185.108us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 631.490s 7962.106us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 117.030s 4401.772us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 117.030s 4401.772us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 192.900s 3450.654us 1 1 100.00
chip_sw_sleep_pin_wake 1 1 100.00
chip_sw_sleep_pin_wake 351.580s 6364.290us 1 1 100.00
chip_sw_sleep_pin_retention 1 1 100.00
chip_sw_sleep_pin_retention 160.760s 3999.053us 1 1 100.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 106.520s 2767.788us 1 1 100.00
chip_tap_straps_testunlock0 292.200s 6177.707us 1 1 100.00
chip_tap_straps_rma 207.820s 4471.119us 1 1 100.00
chip_tap_straps_prod 510.520s 8707.095us 1 1 100.00
chip_sw_pattgen_ios 1 1 100.00
chip_sw_pattgen_ios 192.470s 3171.954us 1 1 100.00
chip_sw_sleep_pwm_pulses 1 1 100.00
chip_sw_sleep_pwm_pulses 855.090s 10162.113us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 522.980s 6484.838us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 522.980s 6484.838us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 642.320s 8161.262us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 654.550s 9537.467us 0 1 0.00
chip_sw_ast_sys_clk_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 349.160s 4134.682us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 667.270s 6509.206us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3529.830s 19005.379us 1 1 100.00
chip_sw_aes_enc_jitter_en 149.460s 2640.416us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 808.940s 7884.524us 1 1 100.00
chip_sw_hmac_enc_jitter_en 170.450s 2996.087us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1114.390s 9163.925us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 203.940s 3318.682us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 295.380s 4098.190us 1 1 100.00
chip_sw_clkmgr_jitter 157.410s 2884.629us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 191.000s 3046.707us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 2 2 100.00
chip_sw_sensor_ctrl_alert 464.190s 6449.873us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 229.690s 4919.516us 1 1 100.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 161.840s 2300.869us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 229.690s 4919.516us 1 1 100.00
chip_sw_smoketest 17 17 100.00
chip_sw_flash_scrambling_smoketest 179.840s 3106.811us 1 1 100.00
chip_sw_aes_smoketest 169.870s 3108.280us 1 1 100.00
chip_sw_aon_timer_smoketest 182.140s 2768.886us 1 1 100.00
chip_sw_clkmgr_smoketest 178.260s 3825.277us 1 1 100.00
chip_sw_csrng_smoketest 132.460s 2751.906us 1 1 100.00
chip_sw_entropy_src_smoketest 693.640s 6469.794us 1 1 100.00
chip_sw_gpio_smoketest 167.640s 2952.377us 1 1 100.00
chip_sw_hmac_smoketest 180.190s 3007.236us 1 1 100.00
chip_sw_kmac_smoketest 214.990s 3384.179us 1 1 100.00
chip_sw_otbn_smoketest 997.130s 8758.859us 1 1 100.00
chip_sw_pwrmgr_smoketest 249.030s 5282.024us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 339.950s 7025.670us 1 1 100.00
chip_sw_rv_plic_smoketest 119.770s 3334.506us 1 1 100.00
chip_sw_rv_timer_smoketest 152.500s 2817.663us 1 1 100.00
chip_sw_rstmgr_smoketest 138.890s 2556.385us 1 1 100.00
chip_sw_sram_ctrl_smoketest 134.900s 3001.255us 1 1 100.00
chip_sw_uart_smoketest 138.780s 2748.141us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 155.010s 3326.063us 1 1 100.00
chip_sw_rom_functests 0 1 0.00
rom_keymgr_functest 341.490s 5138.014us 0 1 0.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 7590.190s 64351.215us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 2594.720s 17031.977us 1 1 100.00
chip_sw_rom_raw_unlock 1 1 100.00
rom_raw_unlock 162.940s 4983.512us 1 1 100.00
chip_sw_power_idle_load 0 1 0.00
chip_sw_power_idle_load 166.560s 3252.160us 0 1 0.00
chip_sw_power_sleep_load 0 1 0.00
chip_sw_power_sleep_load 191.890s 3031.300us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 6989.060s 55860.432us 1 1 100.00
chip_sw_inject_scramble_seed 1 1 100.00
chip_sw_inject_scramble_seed 7164.530s 58647.081us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 62.090s 2499.285us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 62.090s 2499.285us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
chip_csr_aliasing 3456.510s 27978.691us 1 1 100.00
chip_same_csr_outstanding 3420.880s 29772.587us 1 1 100.00
chip_csr_hw_reset 148.900s 5231.599us 1 1 100.00
chip_csr_rw 320.240s 5634.833us 1 1 100.00
tl_d_partial_access 4 4 100.00
chip_csr_aliasing 3456.510s 27978.691us 1 1 100.00
chip_same_csr_outstanding 3420.880s 29772.587us 1 1 100.00
chip_csr_hw_reset 148.900s 5231.599us 1 1 100.00
chip_csr_rw 320.240s 5634.833us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 31.530s 639.518us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 5.590s 55.756us 1 1 100.00
xbar_smoke_large_delays 56.090s 8771.257us 1 1 100.00
xbar_smoke_slow_rsp 36.840s 3918.900us 1 1 100.00
xbar_random_zero_delays 34.130s 647.819us 1 1 100.00
xbar_random_large_delays 75.690s 12630.296us 1 1 100.00
xbar_random_slow_rsp 153.330s 16861.603us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 4.170s 20.392us 1 1 100.00
xbar_error_and_unmapped_addr 5.760s 35.382us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 33.170s 1538.999us 1 1 100.00
xbar_error_and_unmapped_addr 5.760s 35.382us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 86.790s 3154.228us 1 1 100.00
xbar_access_same_device_slow_rsp 421.170s 47109.276us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 5.800s 76.870us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 207.250s 10140.691us 1 1 100.00
xbar_stress_all_with_error 93.480s 1714.483us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 51.260s 173.911us 1 1 100.00
xbar_stress_all_with_reset_error 150.260s 3018.806us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 2594.720s 17031.977us 1 1 100.00
rom_e2e_shutdown_output 1 1 100.00
rom_e2e_shutdown_output 2222.780s 25700.026us 1 1 100.00
rom_e2e_shutdown_exception_c 1 1 100.00
rom_e2e_shutdown_exception_c 2563.840s 17619.275us 1 1 100.00
rom_e2e_boot_policy_valid 5 15 33.33
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 2144.970s 12466.183us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 2531.470s 15966.173us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 2700.370s 15660.863us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 2623.770s 16827.966us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 2545.510s 15273.427us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 16.810s 10.280us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 16.850s 10.160us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 17.370s 10.360us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 20.330s 10.100us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 16.340s 10.220us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 16.430s 10.180us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 16.300s 10.160us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 16.440s 10.140us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 16.220s 10.180us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 16.470s 10.200us 0 1 0.00
rom_e2e_sigverify_always 0 15 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 16.340s 10.120us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 17.080s 10.120us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 16.420s 10.360us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 17.720s 10.300us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 16.700s 10.400us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 16.650s 10.260us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 16.970s 10.160us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 16.820s 10.120us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 17.050s 10.280us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 16.790s 10.240us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 16.300s 10.300us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 16.200s 10.340us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 16.560s 10.280us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 16.770s 10.360us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 19.170s 10.100us 0 1 0.00
rom_e2e_asm_init 5 5 100.00
rom_e2e_asm_init_test_unlocked0 2058.470s 12669.226us 1 1 100.00
rom_e2e_asm_init_dev 2441.860s 16598.768us 1 1 100.00
rom_e2e_asm_init_prod 2474.210s 16302.415us 1 1 100.00
rom_e2e_asm_init_prod_end 2414.160s 15491.097us 1 1 100.00
rom_e2e_asm_init_rma 2349.860s 15525.923us 1 1 100.00
rom_e2e_keymgr_init 3 3 100.00
rom_e2e_keymgr_init_rom_ext_meas 4244.990s 29615.779us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_no_meas 4317.440s 30425.853us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 4332.330s 32943.472us 1 1 100.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 2462.180s 16905.640us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2942.570s 35517.267us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2942.570s 35517.267us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 168.280s 3401.352us 1 1 100.00
chip_sw_aes_enc_jitter_en 149.460s 2640.416us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 136.790s 3283.325us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 155.050s 3105.216us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_sideload_aes 650.030s 7091.941us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 179.910s 3495.992us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 321.360s 4852.863us 1 1 100.00
chip_sw_all_escalation_resets 1 1 100.00
chip_sw_all_escalation_resets 385.850s 6404.490us 1 1 100.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 542.920s 5318.226us 1 1 100.00
chip_plic_all_irqs_10 288.940s 4102.329us 1 1 100.00
chip_plic_all_irqs_20 331.610s 4237.086us 1 1 100.00
chip_sw_alert_handler_entropy 1 1 100.00
chip_sw_alert_handler_entropy 202.520s 3387.345us 1 1 100.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 1177.620s 14767.357us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 308.500s 5013.982us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 170.000s 3112.362us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0.000s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 936.760s 7394.689us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 948.160s 7456.317us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 807.270s 8265.774us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 8101.050s 255736.755us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 222.890s 3772.251us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 249.030s 5282.024us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 222.890s 3772.251us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 395.080s 7572.935us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 395.080s 7572.935us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 282.950s 7961.589us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 374.760s 5232.683us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 587.880s 5590.074us 1 1 100.00
chip_sw_aes_idle 155.050s 3105.216us 1 1 100.00
chip_sw_hmac_enc_idle 194.650s 2835.039us 1 1 100.00
chip_sw_kmac_idle 190.950s 3025.421us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 353.030s 5673.078us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 329.940s 4896.153us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 390.920s 5227.719us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 314.260s 4896.926us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 946.370s 11357.677us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 373.700s 4561.487us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 322.270s 4411.894us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 399.140s 4160.108us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 374.290s 4808.272us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 392.340s 4093.068us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 361.270s 4585.703us 1 1 100.00
chip_sw_ast_clk_outputs 642.320s 8161.262us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 574.280s 10084.352us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 399.140s 4160.108us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 374.290s 4808.272us 1 1 100.00
chip_sw_clkmgr_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 349.160s 4134.682us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 667.270s 6509.206us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3529.830s 19005.379us 1 1 100.00
chip_sw_aes_enc_jitter_en 149.460s 2640.416us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 808.940s 7884.524us 1 1 100.00
chip_sw_hmac_enc_jitter_en 170.450s 2996.087us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1114.390s 9163.925us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 203.940s 3318.682us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 295.380s 4098.190us 1 1 100.00
chip_sw_clkmgr_jitter 157.410s 2884.629us 1 1 100.00
chip_sw_clkmgr_extended_range 11 11 100.00
chip_sw_clkmgr_jitter_reduced_freq 129.400s 3154.380us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 423.380s 5166.137us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 682.300s 8144.227us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 3253.670s 25056.603us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 170.050s 3732.773us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 184.330s 3289.599us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 807.400s 9810.470us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 194.590s 3352.995us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 395.030s 5564.601us 1 1 100.00
chip_sw_flash_init_reduced_freq 1271.440s 25505.449us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 1425.510s 12591.431us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 642.320s 8161.262us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 1 1 100.00
chip_sw_clkmgr_sleep_frequency 313.580s 5025.746us 1 1 100.00
chip_sw_clkmgr_reset_frequency 1 1 100.00
chip_sw_clkmgr_reset_frequency 267.850s 3754.553us 1 1 100.00
chip_sw_clkmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 385.850s 6404.490us 1 1 100.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 936.760s 7394.689us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 662.440s 5309.645us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 0 1 0.00
chip_sw_csrng_fuse_en_sw_app_read_test 136.490s 3048.467us 0 1 0.00
chip_sw_csrng_lc_hw_debug_en 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 428.040s 5658.026us 1 1 100.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 190.030s 2976.257us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 3791.640s 23144.009us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 115.560s 2517.383us 1 1 100.00
chip_sw_edn_entropy_reqs 691.360s 6824.187us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 115.560s 2517.383us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 662.440s 5309.645us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 112.070s 2704.986us 1 1 100.00
chip_sw_flash_init 1 1 100.00
chip_sw_flash_init 1048.740s 20690.035us 1 1 100.00
chip_sw_flash_host_access 2 2 100.00
chip_sw_flash_ctrl_access 601.460s 5459.103us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 667.270s 6509.206us 1 1 100.00
chip_sw_flash_ctrl_ops 2 2 100.00
chip_sw_flash_ctrl_ops 362.960s 3893.135us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 349.160s 4134.682us 1 1 100.00
chip_sw_flash_rma_unlocked 1 1 100.00
chip_sw_flash_rma_unlocked 3643.100s 43103.248us 1 1 100.00
chip_sw_flash_scramble 1 1 100.00
chip_sw_flash_init 1048.740s 20690.035us 1 1 100.00
chip_sw_flash_idle_low_power 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 198.810s 3527.022us 1 1 100.00
chip_sw_flash_keymgr_seeds 1 1 100.00
chip_sw_keymgr_key_derivation 722.540s 7281.148us 1 1 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 157.430s 3458.406us 0 1 0.00
chip_sw_flash_creator_seed_wipe_on_rma 1 1 100.00
chip_sw_flash_rma_unlocked 3643.100s 43103.248us 1 1 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 157.430s 3458.406us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 157.430s 3458.406us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_wr_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 157.430s 3458.406us 0 1 0.00
chip_sw_flash_lc_seed_hw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 157.430s 3458.406us 0 1 0.00
chip_sw_flash_lc_escalate_en 1 1 100.00
chip_sw_all_escalation_resets 385.850s 6404.490us 1 1 100.00
chip_sw_flash_prim_tl_access 1 1 100.00
chip_prim_tl_access 94.880s 5182.250us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 574.060s 5500.154us 1 1 100.00
chip_sw_flash_ctrl_escalation_reset 1 1 100.00
chip_sw_flash_crash_alert 418.700s 6056.244us 1 1 100.00
chip_sw_flash_ctrl_write_clear 1 1 100.00
chip_sw_flash_crash_alert 418.700s 6056.244us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 182.040s 2360.582us 1 1 100.00
chip_sw_hmac_enc_jitter_en 170.450s 2996.087us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 194.650s 2835.039us 1 1 100.00
chip_sw_hmac_all_configurations 1 1 100.00
chip_sw_hmac_oneshot 1691.250s 11884.775us 1 1 100.00
chip_sw_hmac_multistream_mode 1 1 100.00
chip_sw_hmac_multistream 691.190s 5874.370us 1 1 100.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 416.620s 5259.819us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 459.360s 5414.201us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 450.790s 5411.568us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 297.300s 4605.902us 1 1 100.00
chip_sw_keymgr_key_derivation 2 2 100.00
chip_sw_keymgr_key_derivation 722.540s 7281.148us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1114.390s 9163.925us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1 1 100.00
chip_sw_keymgr_sideload_kmac 1505.490s 11122.282us 1 1 100.00
chip_sw_keymgr_sideload_aes 1 1 100.00
chip_sw_keymgr_sideload_aes 650.030s 7091.941us 1 1 100.00
chip_sw_keymgr_sideload_otbn 1 1 100.00
chip_sw_keymgr_sideload_otbn 2454.030s 13675.971us 1 1 100.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 157.500s 2563.843us 1 1 100.00
chip_sw_kmac_mode_kmac 162.070s 3334.429us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 203.940s 3318.682us 1 1 100.00
chip_sw_kmac_app_keymgr 1 1 100.00
chip_sw_keymgr_key_derivation 722.540s 7281.148us 1 1 100.00
chip_sw_kmac_app_lc 1 1 100.00
chip_sw_lc_ctrl_transition 822.910s 12468.120us 1 1 100.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 133.750s 2382.814us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 1038.320s 8011.411us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 190.950s 3025.421us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 321.360s 4852.863us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 106.520s 2767.788us 1 1 100.00
chip_tap_straps_rma 207.820s 4471.119us 1 1 100.00
chip_tap_straps_prod 510.520s 8707.095us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 183.630s 2585.974us 1 1 100.00
chip_sw_lc_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 822.910s 12468.120us 1 1 100.00
chip_sw_lc_ctrl_transitions 1 1 100.00
chip_sw_lc_ctrl_transition 822.910s 12468.120us 1 1 100.00
chip_sw_lc_ctrl_kmac_req 1 1 100.00
chip_sw_lc_ctrl_transition 822.910s 12468.120us 1 1 100.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_key_derivation_prod 612.480s 7196.657us 1 1 100.00
chip_sw_lc_ctrl_broadcast 19 22 86.36
chip_prim_tl_access 94.880s 5182.250us 1 1 100.00
chip_rv_dm_lc_disabled 35.130s 1892.718us 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 157.430s 3458.406us 0 1 0.00
chip_sw_flash_rma_unlocked 3643.100s 43103.248us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 212.060s 3420.315us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 411.260s 5606.106us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 517.450s 7217.057us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 625.470s 8173.170us 0 1 0.00
chip_sw_lc_ctrl_transition 822.910s 12468.120us 1 1 100.00
chip_sw_keymgr_key_derivation 722.540s 7281.148us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 418.370s 8793.350us 1 1 100.00
chip_sw_sram_ctrl_execution_main 660.780s 9221.930us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 574.280s 10084.352us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 373.700s 4561.487us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 322.270s 4411.894us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 399.140s 4160.108us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 374.290s 4808.272us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 392.340s 4093.068us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 361.270s 4585.703us 1 1 100.00
chip_tap_straps_dev 106.520s 2767.788us 1 1 100.00
chip_tap_straps_rma 207.820s 4471.119us 1 1 100.00
chip_tap_straps_prod 510.520s 8707.095us 1 1 100.00
chip_lc_scrap 4 4 100.00
chip_sw_lc_ctrl_rma_to_scrap 160.310s 3657.253us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 82.960s 2914.433us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 75.100s 3295.135us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 163.950s 3455.216us 1 1 100.00
chip_lc_test_locked 1 2 50.00
chip_rv_dm_lc_disabled 35.130s 1892.718us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 1658.150s 32439.263us 1 1 100.00
chip_sw_lc_walkthrough 2 5 40.00
chip_sw_lc_walkthrough_dev 653.350s 8620.589us 0 1 0.00
chip_sw_lc_walkthrough_prod 649.950s 9113.363us 0 1 0.00
chip_sw_lc_walkthrough_prodend 557.940s 9407.165us 1 1 100.00
chip_sw_lc_walkthrough_rma 401.750s 7424.058us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 1658.150s 32439.263us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 3 3 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 70.330s 2274.659us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 61.240s 2160.065us 1 1 100.00
rom_volatile_raw_unlock 56.210s 1902.121us 1 1 100.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 3538.960s 17534.791us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3529.830s 19005.379us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 587.880s 5590.074us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 587.880s 5590.074us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 587.880s 5590.074us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 288.980s 3706.164us 1 1 100.00
chip_otp_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 822.910s 12468.120us 1 1 100.00
chip_sw_otp_ctrl_keys 5 5 100.00
chip_sw_flash_init 1048.740s 20690.035us 1 1 100.00
chip_sw_otbn_mem_scramble 288.980s 3706.164us 1 1 100.00
chip_sw_keymgr_key_derivation 722.540s 7281.148us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 432.410s 5217.799us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 168.710s 3323.020us 1 1 100.00
chip_sw_otp_ctrl_entropy 5 5 100.00
chip_sw_flash_init 1048.740s 20690.035us 1 1 100.00
chip_sw_otbn_mem_scramble 288.980s 3706.164us 1 1 100.00
chip_sw_keymgr_key_derivation 722.540s 7281.148us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 432.410s 5217.799us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 168.710s 3323.020us 1 1 100.00
chip_sw_otp_ctrl_program 1 1 100.00
chip_sw_lc_ctrl_transition 822.910s 12468.120us 1 1 100.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 427.470s 5207.331us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 183.630s 2585.974us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 5 6 83.33
chip_prim_tl_access 94.880s 5182.250us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 212.060s 3420.315us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 411.260s 5606.106us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 517.450s 7217.057us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 625.470s 8173.170us 0 1 0.00
chip_sw_lc_ctrl_transition 822.910s 12468.120us 1 1 100.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 94.880s 5182.250us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 808.810s 8333.132us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 1 1 100.00
chip_sw_pwrmgr_full_aon_reset 304.460s 7295.030us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1027.320s 23153.019us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 268.410s 7808.152us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 0 1 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 324.290s 7295.605us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 489.450s 6155.294us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1027.230s 23289.431us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 1 2 50.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 976.990s 15632.030us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 395.080s 7572.935us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 789.260s 12560.292us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 417.100s 6187.787us 1 1 100.00
chip_sw_pwrmgr_aon_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_full_aon_reset 304.460s 7295.030us 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 313.750s 4614.202us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 2094.260s 28867.516us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 300.260s 6318.689us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 281.800s 4862.106us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1559.000s 22670.215us 1 1 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 725.350s 7816.950us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 708.170s 10041.569us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1547.700s 25355.254us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 210.380s 3572.092us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 385.850s 6404.490us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 418.370s 8793.350us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 418.370s 8793.350us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 4 4 100.00
chip_sw_pwrmgr_all_reset_reqs 708.170s 10041.569us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1559.000s 22670.215us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 417.100s 6187.787us 1 1 100.00
chip_sw_pwrmgr_smoketest 249.030s 5282.024us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 205.110s 3917.086us 1 1 100.00
chip_sw_rstmgr_cpu_info 0 1 0.00
chip_sw_rstmgr_cpu_info 262.770s 3518.824us 0 1 0.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 232.460s 4212.501us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 1177.620s 14767.357us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 173.460s 3252.458us 1 1 100.00
chip_sw_rstmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 385.850s 6404.490us 1 1 100.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 948.160s 7456.317us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 520.590s 4941.884us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 501.480s 5400.215us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 184.910s 2955.174us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 168.710s 3323.020us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 0 1 0.00
chip_sw_rstmgr_cpu_info 262.770s 3518.824us 0 1 0.00
chip_sw_rv_core_ibex_double_fault 0 1 0.00
chip_sw_rstmgr_cpu_info 262.770s 3518.824us 0 1 0.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 518.860s 9577.036us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 1019.430s 14544.647us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 205.110s 3917.086us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 168.200s 2674.274us 0 1 0.00
chip_rv_dm_access_after_wakeup 1 1 100.00
chip_sw_rv_dm_access_after_wakeup 311.250s 7590.983us 1 1 100.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 207.820s 4471.119us 1 1 100.00
chip_rv_dm_lc_disabled 0 1 0.00
chip_rv_dm_lc_disabled 35.130s 1892.718us 0 1 0.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 542.920s 5318.226us 1 1 100.00
chip_plic_all_irqs_10 288.940s 4102.329us 1 1 100.00
chip_plic_all_irqs_20 331.610s 4237.086us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 118.620s 2635.383us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 192.030s 3772.273us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 2594.720s 17031.977us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 434.840s 6576.467us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 222.660s 3761.652us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 223.800s 3420.869us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 144.200s 2483.142us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 432.410s 5217.799us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 295.380s 4098.190us 1 1 100.00
chip_sw_sleep_sram_ret_contents 2 2 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 414.710s 7420.771us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 466.490s 7985.838us 1 1 100.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 660.780s 9221.930us 1 1 100.00
chip_sw_sram_lc_escalation 2 2 100.00
chip_sw_all_escalation_resets 385.850s 6404.490us 1 1 100.00
chip_sw_data_integrity_escalation 522.980s 6484.838us 1 1 100.00
chip_sw_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 725.350s 7816.950us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1062.900s 24721.992us 1 1 100.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 184.930s 2785.869us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 250.170s 3592.477us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 352.640s 4689.589us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 1 1 100.00
chip_sw_sysrst_ctrl_reset 1062.900s 24721.992us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_reset 1 1 100.00
chip_sw_sysrst_ctrl_reset 1062.900s 24721.992us 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2163.570s 20628.963us 1 1 100.00
chip_sw_sysrst_ctrl_flash_wp_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2163.570s 20628.963us 1 1 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 365.500s 6521.676us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2942.570s 35517.267us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 160.420s 3027.341us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 124.080s 2624.619us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 255.100s 3827.704us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 332.700s 4308.586us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 1013.890s 8798.640us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 4908.180s 32217.149us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 1875.920s 11710.975us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 127.580s 2694.939us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 164.630s 2867.916us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 0 1 0.00
chip_sw_rv_core_ibex_lockstep_glitch 101.760s 2087.307us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 9157.470s 71489.750us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 1043.260s 6514.763us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 163.760s 3755.926us 0 1 0.00
rom_e2e_jtag_debug_dev 181.330s 4000.766us 0 1 0.00
rom_e2e_jtag_debug_rma 140.480s 4207.547us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 63.310s 1888.709us 0 1 0.00
rom_e2e_jtag_inject_dev 59.820s 2570.000us 0 1 0.00
rom_e2e_jtag_inject_rma 59.620s 2501.330us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 11.579s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 1 0.00
chip_sw_clkmgr_jitter_frequency 256.970s 3202.707us 0 1 0.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 312.880s 3184.282us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 528.090s 4073.979us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 1366.950s 10026.191us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 232.070s 2491.966us 1 1 100.00
chip_sw_flash_memory_protection 1 1 100.00
chip_sw_flash_ctrl_mem_protection 564.420s 5119.664us 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 63.850s 2584.196us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 168.270s 2985.068us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 1 1 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 344.640s 6299.216us 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 289.230s 4997.187us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 708.170s 10041.569us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 163.760s 3755.926us 0 1 0.00
rom_e2e_jtag_debug_dev 181.330s 4000.766us 0 1 0.00
rom_e2e_jtag_debug_rma 140.480s 4207.547us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 436.790s 5879.655us 1 1 100.00
chip_sw_plic_alerts 1 1 100.00
chip_sw_all_escalation_resets 385.850s 6404.490us 1 1 100.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 5259.640s 38070.370us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 5259.640s 38070.370us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 186.780s 3750.122us 1 1 100.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 339.610s 3520.866us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 3190.090s 19191.467us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 6 8 75.00
chip_sival_flash_info_access 178.570s 3388.968us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 435.120s 5403.238us 1 1 100.00
chip_sw_otp_ctrl_rot_auth_config 5.320s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 119.690s 2832.168us 1 1 100.00
chip_sw_otp_ctrl_descrambling 237.290s 3327.101us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 241.900s 3899.209us 1 1 100.00
chip_sw_pwrmgr_sleep_wake_5_bug 8.918s 0.000us 0 1 0.00
chip_sw_flash_ctrl_write_clear 193.730s 3140.992us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *).
chip_tl_errors 85529286617175692264201581137959734205326808610901767224691599389937175461441 217
UVM_ERROR @ 2499.285450 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@37995) { a_addr: 'h10568 a_data: 'h6c7e0894 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3f a_opcode: 'h4 a_user: 'h1b65e d_param: 'h0 d_source: 'h3f d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2499.285450 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rstmgr_cpu_info 21496458012899814567454108325074813060813878983041276851802266952093838879056 333
UVM_ERROR @ 3518.824168 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 0, but saw 1).
TL item was: req: (cip_tl_seq_item@106615) { a_addr: 'h8 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h0 a_user: 'h259aa d_param: 'h0 d_source: 'h0 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h1f2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{}.
UVM_INFO @ 3518.824168 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:649) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch
chip_rv_dm_lc_disabled 25151246343377933535273104285944341108086367022316493698808187245015368314180 215
UVM_ERROR @ 1892.717947 us: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x10764 read out mismatch
UVM_INFO @ 1892.717947 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
chip_sw_spi_device_pass_through_collision 47302987225040379109252357638509702014689101434020858284647029241747871514964 320
UVM_ERROR @ 3761.652035 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
UVM_INFO @ 3761.652035 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_flash_ctrl_lc_rw_en 62826272666287748540156705436387593719339678421246289625747482195946574491958 309
UVM_ERROR @ 3458.405920 us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 35 is asserted but not expected
UVM_INFO @ 3458.405920 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *
chip_sw_otp_ctrl_lc_signals_rma 26309407719814664187442537001554165814959514774262663310290443400115122766306 342
UVM_ERROR @ 8173.169890 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0
UVM_INFO @ 8173.169890 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
chip_sw_otp_ctrl_escalation 91557776514289094743799642242844395284231531715251120357800525142452111163088 316
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 2985.067560 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2985.067560 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_csrng_fuse_en_sw_app_read_test 9739673038526390316711938296714710438087135695655682213883430324482611802008 312
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 3048.466980 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3048.466980 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode
chip_sw_otp_ctrl_rot_auth_config 35195502097597508486801217260598057491167622858894560237339951727236250092024 282
UVM_FATAL @ 0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.24.vmem could not be opened for r mode
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_lc_walkthrough_dev 17809271397825364517500275328426676427099347452411751237322101829793960921592 369
UVM_ERROR @ 8620.589464 us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 47 is asserted but not expected
UVM_INFO @ 8620.589464 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 13432495451355458671844735695810011057555892790582394667940074468750924489605 369
UVM_ERROR @ 9113.363348 us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 47 is asserted but not expected
UVM_INFO @ 9113.363348 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 30834828087164677971560234698328681518635506340025421115581345182842668688887 341
UVM_ERROR @ 7424.057736 us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 47 is asserted but not expected
UVM_INFO @ 7424.057736 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))'
chip_sw_pwrmgr_deep_sleep_por_reset 65482453596474508820095816421936647929856129913590857073415722480234579536751 325
Offending '(rstreqs[0] && (reset_cause == HwReq))'
UVM_ERROR @ 7295.604500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7295.604500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aon_timer_wdog_bite_reset 109672705221522042120943836798981852288079034679889611285164256794425376810141 319
Offending '(rstreqs[1] && (reset_cause == HwReq))'
UVM_ERROR @ 7572.935000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7572.935000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 15262715470171280914076587222073760387617328238754304503767332076459822947192 332
UVM_ERROR @ 35517.266898 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns
UVM_INFO @ 35517.266898 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *!
chip_sw_alert_test 74991124363147883306812206362501628100713048648984886415794489519297735736014 307
UVM_ERROR @ 3495.992054 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 43!
UVM_INFO @ 3495.992054 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
chip_sw_alert_handler_lpg_sleep_mode_alerts 11878846536799528678823859698860626703818533918531834891366391096028471417091 308
UVM_ERROR @ 3112.361843 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3112.361843 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes
chip_sw_alert_handler_lpg_sleep_mode_pings 54695523338541387161632059070197401498602884635479590495290578157684331484038 None
Job timed out after 240 minutes
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_clkmgr_jitter_frequency 115198517090070057717071701074236251309297713581746434699249054535283491478044 343
UVM_ERROR @ 3202.706867 us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 25 is asserted but not expected
UVM_INFO @ 3202.706867 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job returned non-zero exit code
chip_sw_pwrmgr_sleep_wake_5_bug 87221246675980921830315574025670062008111496927388136838996753261974015685494 None
---- STDERR ----
Another command (pid=1915710) is running. Waiting for it to complete on the server (server_pid=924987)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 99417449447213789442317492208653370421184917034107261771935676143756664847101 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Error-[NOA] Null object access
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 42238221845415936776456666046744959773884039448405415557745511838457657277142 327
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_test_unlocked0 114480148185585047236263890694448033672260538846043846449507908031189861610118 319
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_dev 15203134549972916501510310492637466407667488387744028072980501069580390417277 319
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 64271953142086517697169051208208308929553253614621860485882675623068419262903 305
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 15672991209354408837481739469472027205843575658791543712385170695990016289736 305
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 81392267862687129313924961302928587852588467928913954074852101068680823175270 305
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:738) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation.
chip_sw_rv_core_ibex_lockstep_glitch 51879905177931296155725279170421198901167311183696404984197963619750747182436 327
UVM_FATAL @ 2087.306948 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:738) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
UVM_INFO @ 2087.306948 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_idle_load 101765304590607793281299547753335147447220918311440219795085853606163092784946 312
UVM_ERROR @ 3252.160000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH3 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 3252.160000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_sleep_load 15922805338260990121389121068766043911053662541534647492527469584770492790200 318
UVM_ERROR @ 3031.300000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH3 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 3031.300000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *
chip_sw_ast_clk_rst_inputs 47327922848515286697103100045755637439652482955895457287104626572202142283078 327
UVM_ERROR @ 9537.466895 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ 4294967271 expected to fire. Actual IRQ state = 1
UVM_INFO @ 9537.466895 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 4752255533383763090235862162379353207151064534430472802579682927754037810091 350
UVM_FATAL @ 10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_dev 103433086448900422945858639953992874076555377315999293756430789649184144445628 350
UVM_FATAL @ 10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_prod 18950287068498416053611736237607123976022906403081630207161108742559623805632 351
UVM_FATAL @ 10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 41030414944010441662440135094923395998875823121034332666699286322782846857640 351
UVM_FATAL @ 10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_rma 80946992267849602978876290575998739846533368547466418854633805726127799903183 351
UVM_FATAL @ 10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 23855113133044411918818577617774024924554837289390027893871828001364720314735 347
UVM_FATAL @ 10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_dev 91738180977176099438702531490004989762679336043365541001978071684091401816229 346
UVM_FATAL @ 10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_prod 109401046994050469096939245576478494373409583900982042085551859656764207647775 348
UVM_FATAL @ 10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 77667860635490121896586594601197785972353681355934283370377352300832728857829 346
UVM_FATAL @ 10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_rma 3658892023262860040934780498863604621546277045554302603625249281342862893885 349
UVM_FATAL @ 10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod 54475488934792760825692593769116696701025556543669849108694614437896882618240 359
UVM_FATAL @ 10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 9850284604416396665127588802603134274308599618263525420513958330717371966619 357
UVM_FATAL @ 10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_rma 75910847280462307181248363915610210381433973761412556011499327260069547538031 357
UVM_FATAL @ 10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod 6502448182859645148137228942094483246587464098225232808065876697684738955410 323
UVM_FATAL @ 10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 57508808228339125381022228355030272494457132204446735241141176216855116619394 322
UVM_FATAL @ 10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_rma 110553062515900085077021352105883857671004848466095300285763206415059732139268 322
UVM_FATAL @ 10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 94332409103982812049246285466072220491146646073752676163602200670727915426894 361
UVM_FATAL @ 10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 58358448517213983162903060516626975370898341170322436789972771727013439450211 325
UVM_FATAL @ 10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_dev 4748071406627188075781436631818115745988892452088820352592720886746726828228 359
UVM_FATAL @ 10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_dev 90953839867846160481143107122640277156144886065809247984091891487872221897909 323
UVM_FATAL @ 10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 95454849830512503488995704567997283929614424632229244845128732839540477375178 323
UVM_FATAL @ 10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_dev 109280968697144946994665389645273372153709609011408697793813627207206685800802 322
UVM_FATAL @ 10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_prod 5886035201369311663808275674357619486858856018401745005543496510418719511590 322
UVM_FATAL @ 10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 600693268356593528163812179443613732256196425360018311498135318389707978132 323
UVM_FATAL @ 10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_rma 43952779782667359216510449936048375559799638016159589682895350340444154542522 322
UVM_FATAL @ 10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_rv_debugger.sv:784) [debugger] Index * appears to be out of bounds
rom_e2e_jtag_debug_rma 39257538761317012000551365146596876764970370313958763161349458052849325253868 318
UVM_ERROR @ 4207.547419 us: (jtag_rv_debugger.sv:784) [debugger] Index 3 appears to be out of bounds
UVM_INFO @ 4207.547419 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)'
rom_keymgr_functest 70050977734943804556113914484608498341761041936912350245575676780601853840086 327
Offending '$stable(key_data_i)'
UVM_ERROR @ 5138.014304 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 5138.014304 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---