Simulation Results: clkmgr

 
08/04/2026 18:06:49 DVSim: v1.17.3 sha: 007b0cf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.85 %
  • code
  • 98.22 %
  • assert
  • 95.76 %
  • func
  • 84.56 %
  • line
  • 98.99 %
  • branch
  • 98.57 %
  • cond
  • 94.36 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.750s 16.545us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.680s 41.948us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.710s 58.155us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 2.660s 361.372us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.310s 79.182us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 0.910s 59.975us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.710s 58.155us 1 1 100.00
clkmgr_csr_aliasing 1.310s 79.182us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.670s 25.532us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.860s 53.018us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.730s 17.455us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.610s 16.892us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.750s 16.545us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 7.120s 1522.812us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 4.960s 1583.398us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 7.120s 1522.812us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 10.940s 4234.492us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.880s 130.338us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.500s 70.761us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.500s 70.761us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.680s 41.948us 1 1 100.00
clkmgr_csr_rw 0.710s 58.155us 1 1 100.00
clkmgr_csr_aliasing 1.310s 79.182us 1 1 100.00
clkmgr_same_csr_outstanding 0.850s 28.809us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.680s 41.948us 1 1 100.00
clkmgr_csr_rw 0.710s 58.155us 1 1 100.00
clkmgr_csr_aliasing 1.310s 79.182us 1 1 100.00
clkmgr_same_csr_outstanding 0.850s 28.809us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 1.000s 74.683us 0 1 0.00
clkmgr_tl_intg_err 2.350s 446.546us 1 1 100.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 2.720s 981.646us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 2.720s 981.646us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 2.720s 981.646us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 2.720s 981.646us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 2.700s 509.224us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 2.350s 446.546us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 7.120s 1522.812us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 4.960s 1583.398us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 2.720s 981.646us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.670s 32.734us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.790s 76.162us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.690s 28.406us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 0 1 0.00
clkmgr_clk_handshake_intersig_mubi 0.620s 4.109us 0 1 0.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.780s 73.091us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.710s 58.155us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 1.000s 74.683us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.710s 58.155us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.710s 58.155us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 1.000s 74.683us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 1.250s 260.260us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 27.020s 4888.980us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (clkmgr_extclk_vseq.sv:99) [clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (* [*] vs * [*]) extclk_status mismatch
clkmgr_clk_handshake_intersig_mubi 85752607372455724932757359699347525081811415615516941590410650142530150903869 79
UVM_ERROR @ 4109109 ps: (clkmgr_extclk_vseq.sv:99) [uvm_test_top.env.virtual_sequencer.clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (13 [0xd] vs 9 [0x9]) extclk_status mismatch
UVM_INFO @ 4109109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [clkmgr_common_vseq] expect alert:fatal_fault to fire
clkmgr_sec_cm 3615816644031745257571625774700595730562867403599824926280029287394352778770 127
UVM_ERROR @ 74682709 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire
UVM_INFO @ 74682709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---