Simulation Results: csrng

 
08/04/2026 18:06:49 DVSim: v1.17.3 sha: 007b0cf json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 85.53 %
  • code
  • 92.48 %
  • assert
  • 93.89 %
  • func
  • 70.22 %
  • block
  • 97.18 %
  • line
  • 97.87 %
  • branch
  • 92.92 %
  • toggle
  • 93.44 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 2.000s 16.988us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 35.146us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 71.983us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 8.000s 182.414us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 3.000s 144.954us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 2.000s 108.441us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 71.983us 1 1 100.00
csrng_csr_aliasing 3.000s 144.954us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 3.000s 94.549us 1 1 100.00
alerts 1 1 100.00
csrng_alert 8.000s 697.405us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 43.450us 1 1 100.00
cmds 1 1 100.00
csrng_cmds 155.000s 16464.623us 1 1 100.00
life cycle 1 1 100.00
csrng_cmds 155.000s 16464.623us 1 1 100.00
stress_all 1 1 100.00
csrng_stress_all 3.000s 55.168us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 22.999us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 27.281us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 4.000s 269.055us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 4.000s 269.055us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 35.146us 1 1 100.00
csrng_csr_rw 2.000s 71.983us 1 1 100.00
csrng_csr_aliasing 3.000s 144.954us 1 1 100.00
csrng_same_csr_outstanding 3.000s 159.541us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 35.146us 1 1 100.00
csrng_csr_rw 2.000s 71.983us 1 1 100.00
csrng_csr_aliasing 3.000s 144.954us 1 1 100.00
csrng_same_csr_outstanding 3.000s 159.541us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_tl_intg_err 3.000s 173.086us 1 1 100.00
csrng_sec_cm 3.000s 68.782us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_csr_rw 2.000s 71.983us 1 1 100.00
csrng_regwen 2.000s 21.780us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 8.000s 697.405us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 3.000s 55.168us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 3.000s 94.549us 1 1 100.00
csrng_err 2.000s 43.450us 1 1 100.00
csrng_sec_cm 3.000s 68.782us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 3.000s 94.549us 1 1 100.00
csrng_err 2.000s 43.450us 1 1 100.00
csrng_sec_cm 3.000s 68.782us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 3.000s 94.549us 1 1 100.00
csrng_err 2.000s 43.450us 1 1 100.00
csrng_sec_cm 3.000s 68.782us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 3.000s 94.549us 1 1 100.00
csrng_err 2.000s 43.450us 1 1 100.00
csrng_sec_cm 3.000s 68.782us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 3.000s 94.549us 1 1 100.00
csrng_err 2.000s 43.450us 1 1 100.00
csrng_sec_cm 3.000s 68.782us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 8.000s 697.405us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 3.000s 94.549us 1 1 100.00
csrng_err 2.000s 43.450us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 3.000s 55.168us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 8.000s 697.405us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 3.000s 173.086us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 3.000s 94.549us 1 1 100.00
csrng_err 2.000s 43.450us 1 1 100.00
csrng_sec_cm 3.000s 68.782us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 3.000s 94.549us 1 1 100.00
csrng_err 2.000s 43.450us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 3.000s 94.549us 1 1 100.00
csrng_err 2.000s 43.450us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 3.000s 94.549us 1 1 100.00
csrng_err 2.000s 43.450us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 3.000s 94.549us 1 1 100.00
csrng_err 2.000s 43.450us 1 1 100.00
csrng_sec_cm 3.000s 68.782us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 3.000s 94.549us 1 1 100.00
csrng_err 2.000s 43.450us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 0.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes
csrng_stress_all_with_rand_reset 61037751938245927710968484447970754550349005595432807901551291518782098140398 None
Job timed out after 180 minutes