Simulation Results: edn/edn0

 
08/04/2026 18:06:49 DVSim: v1.17.3 sha: 007b0cf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.73 %
  • code
  • 82.32 %
  • assert
  • 96.31 %
  • func
  • 81.55 %
  • line
  • 97.88 %
  • branch
  • 92.61 %
  • cond
  • 87.58 %
  • toggle
  • 81.93 %
  • FSM
  • 51.61 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.890s 158.819us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.690s 88.001us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.790s 16.158us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.430s 139.511us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 0.870s 16.888us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.820s 161.109us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.790s 16.158us 1 1 100.00
edn_csr_aliasing 0.870s 16.888us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.000s 75.044us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.000s 75.044us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.000s 75.044us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.930s 20.951us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.920s 49.030us 1 1 100.00
errs 1 1 100.00
edn_err 0.900s 19.174us 1 1 100.00
disable 2 2 100.00
edn_disable 0.740s 36.837us 1 1 100.00
edn_disable_auto_req_mode 0.840s 36.520us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.950s 407.129us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.760s 14.889us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.750s 109.086us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.870s 69.988us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.870s 69.988us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.690s 88.001us 1 1 100.00
edn_csr_rw 0.790s 16.158us 1 1 100.00
edn_csr_aliasing 0.870s 16.888us 1 1 100.00
edn_same_csr_outstanding 0.910s 19.543us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.690s 88.001us 1 1 100.00
edn_csr_rw 0.790s 16.158us 1 1 100.00
edn_csr_aliasing 0.870s 16.888us 1 1 100.00
edn_same_csr_outstanding 0.910s 19.543us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 5.630s 2108.127us 1 1 100.00
edn_tl_intg_err 1.720s 168.148us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.920s 50.146us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.920s 49.030us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.630s 2108.127us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.630s 2108.127us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 5.630s 2108.127us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 5.630s 2108.127us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.920s 49.030us 1 1 100.00
edn_sec_cm 5.630s 2108.127us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.920s 49.030us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.720s 168.148us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 43.650s 6275.467us 1 1 100.00