Simulation Results: edn/edn1

 
08/04/2026 18:06:49 DVSim: v1.17.3 sha: 007b0cf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.76 %
  • code
  • 84.32 %
  • assert
  • 96.35 %
  • func
  • 79.62 %
  • line
  • 97.88 %
  • branch
  • 92.64 %
  • cond
  • 89.23 %
  • toggle
  • 95.25 %
  • FSM
  • 46.59 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.800s 23.195us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.710s 24.822us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.730s 26.328us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.670s 266.345us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 0.940s 32.989us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.030s 57.316us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.730s 26.328us 1 1 100.00
edn_csr_aliasing 0.940s 32.989us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 0.960s 32.666us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 0.960s 32.666us 1 1 100.00
genbits 1 1 100.00
edn_genbits 0.960s 32.666us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.710s 34.817us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.850s 159.557us 1 1 100.00
errs 1 1 100.00
edn_err 0.810s 27.654us 1 1 100.00
disable 2 2 100.00
edn_disable 0.720s 14.342us 1 1 100.00
edn_disable_auto_req_mode 0.840s 165.683us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.610s 367.300us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.730s 32.314us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.030s 57.368us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.390s 61.074us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.390s 61.074us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.710s 24.822us 1 1 100.00
edn_csr_rw 0.730s 26.328us 1 1 100.00
edn_csr_aliasing 0.940s 32.989us 1 1 100.00
edn_same_csr_outstanding 0.990s 30.553us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.710s 24.822us 1 1 100.00
edn_csr_rw 0.730s 26.328us 1 1 100.00
edn_csr_aliasing 0.940s 32.989us 1 1 100.00
edn_same_csr_outstanding 0.990s 30.553us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.470s 4457.139us 1 1 100.00
edn_tl_intg_err 1.210s 104.240us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.790s 51.646us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.850s 159.557us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.470s 4457.139us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.470s 4457.139us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.470s 4457.139us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.470s 4457.139us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.850s 159.557us 1 1 100.00
edn_sec_cm 3.470s 4457.139us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.850s 159.557us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.210s 104.240us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 23.000s 6137.639us 1 1 100.00