| V1 |
|
100.00% |
| V2 |
|
98.28% |
| V2S |
|
95.83% |
| V3 |
|
100.00% |
| unmapped |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| flash_ctrl_smoke | 61.280s | 87.781us | 1 | 1 | 100.00 | |
| smoke_hw | 1 | 1 | 100.00 | |||
| flash_ctrl_smoke_hw | 9.360s | 17.436us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| flash_ctrl_csr_hw_reset | 9.140s | 144.843us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| flash_ctrl_csr_rw | 5.640s | 237.914us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| flash_ctrl_csr_bit_bash | 18.710s | 673.625us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| flash_ctrl_csr_aliasing | 37.370s | 2652.059us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| flash_ctrl_csr_mem_rw_with_rand_reset | 5.850s | 170.178us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| flash_ctrl_csr_rw | 5.640s | 237.914us | 1 | 1 | 100.00 | |
| flash_ctrl_csr_aliasing | 37.370s | 2652.059us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| flash_ctrl_mem_walk | 4.750s | 73.102us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| flash_ctrl_mem_partial_access | 4.840s | 18.538us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| sw_op | 1 | 1 | 100.00 | |||
| flash_ctrl_sw_op | 9.570s | 80.620us | 1 | 1 | 100.00 | |
| host_read_direct | 1 | 1 | 100.00 | |||
| flash_ctrl_host_dir_rd | 11.700s | 26.304us | 1 | 1 | 100.00 | |
| rma_hw_if | 3 | 3 | 100.00 | |||
| flash_ctrl_hw_rma | 1501.790s | 195785.807us | 1 | 1 | 100.00 | |
| flash_ctrl_hw_rma_reset | 483.060s | 40127.889us | 1 | 1 | 100.00 | |
| flash_ctrl_lcmgr_intg | 4.950s | 44.540us | 1 | 1 | 100.00 | |
| host_controller_arb | 1 | 1 | 100.00 | |||
| flash_ctrl_host_ctrl_arb | 949.670s | 2026088.285us | 1 | 1 | 100.00 | |
| erase_suspend | 1 | 1 | 100.00 | |||
| flash_ctrl_erase_suspend | 174.690s | 8499.978us | 1 | 1 | 100.00 | |
| program_reset | 1 | 1 | 100.00 | |||
| flash_ctrl_prog_reset | 5.080s | 20.674us | 1 | 1 | 100.00 | |
| full_memory_access | 1 | 1 | 100.00 | |||
| flash_ctrl_full_mem_access | 1943.790s | 1524975.332us | 1 | 1 | 100.00 | |
| rd_buff_eviction | 1 | 1 | 100.00 | |||
| flash_ctrl_rd_buff_evict | 44.400s | 1518.307us | 1 | 1 | 100.00 | |
| rd_buff_eviction_w_ecc | 3 | 3 | 100.00 | |||
| flash_ctrl_rw_evict | 12.750s | 201.595us | 1 | 1 | 100.00 | |
| flash_ctrl_rw_evict_all_en | 10.930s | 39.777us | 1 | 1 | 100.00 | |
| flash_ctrl_re_evict | 14.940s | 148.074us | 1 | 1 | 100.00 | |
| host_arb | 1 | 1 | 100.00 | |||
| flash_ctrl_phy_arb | 111.690s | 347.760us | 1 | 1 | 100.00 | |
| host_interleave | 1 | 1 | 100.00 | |||
| flash_ctrl_phy_arb | 111.690s | 347.760us | 1 | 1 | 100.00 | |
| memory_protection | 1 | 1 | 100.00 | |||
| flash_ctrl_mp_regions | 214.120s | 16786.588us | 1 | 1 | 100.00 | |
| fetch_code | 1 | 1 | 100.00 | |||
| flash_ctrl_fetch_code | 11.720s | 303.262us | 1 | 1 | 100.00 | |
| all_partitions | 1 | 1 | 100.00 | |||
| flash_ctrl_rand_ops | 113.740s | 45.881us | 1 | 1 | 100.00 | |
| error_mp | 1 | 1 | 100.00 | |||
| flash_ctrl_error_mp | 279.780s | 23329.112us | 1 | 1 | 100.00 | |
| error_prog_win | 1 | 1 | 100.00 | |||
| flash_ctrl_error_prog_win | 253.420s | 2743.608us | 1 | 1 | 100.00 | |
| error_prog_type | 1 | 1 | 100.00 | |||
| flash_ctrl_error_prog_type | 881.680s | 2369.750us | 1 | 1 | 100.00 | |
| error_read_seed | 1 | 1 | 100.00 | |||
| flash_ctrl_hw_read_seed_err | 4.930s | 77.136us | 1 | 1 | 100.00 | |
| read_write_overflow | 1 | 1 | 100.00 | |||
| flash_ctrl_oversize_error | 94.610s | 7428.482us | 1 | 1 | 100.00 | |
| flash_ctrl_disable | 1 | 1 | 100.00 | |||
| flash_ctrl_disable | 8.740s | 23.145us | 1 | 1 | 100.00 | |
| flash_ctrl_connect | 1 | 1 | 100.00 | |||
| flash_ctrl_connect | 6.360s | 31.961us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| flash_ctrl_stress_all | 15.310s | 49.548us | 1 | 1 | 100.00 | |
| secret_partition | 2 | 2 | 100.00 | |||
| flash_ctrl_hw_sec_otp | 62.080s | 5687.784us | 1 | 1 | 100.00 | |
| flash_ctrl_otp_reset | 46.760s | 84.782us | 1 | 1 | 100.00 | |
| isolation_partition | 1 | 1 | 100.00 | |||
| flash_ctrl_hw_rma | 1501.790s | 195785.807us | 1 | 1 | 100.00 | |
| interrupts | 3 | 4 | 75.00 | |||
| flash_ctrl_intr_rd | 85.350s | 1300.277us | 1 | 1 | 100.00 | |
| flash_ctrl_intr_wr | 44.980s | 10193.036us | 1 | 1 | 100.00 | |
| flash_ctrl_intr_rd_slow_flash | 162.960s | 8492.710us | 1 | 1 | 100.00 | |
| flash_ctrl_intr_wr_slow_flash | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| invalid_op | 1 | 1 | 100.00 | |||
| flash_ctrl_invalid_op | 41.250s | 1342.657us | 1 | 1 | 100.00 | |
| mid_op_rst | 1 | 1 | 100.00 | |||
| flash_ctrl_mid_op_rst | 30.290s | 1072.104us | 1 | 1 | 100.00 | |
| double_bit_err | 5 | 5 | 100.00 | |||
| flash_ctrl_read_word_sweep_derr | 8.840s | 25.934us | 1 | 1 | 100.00 | |
| flash_ctrl_ro_derr | 76.120s | 712.911us | 1 | 1 | 100.00 | |
| flash_ctrl_rw_derr | 114.080s | 7720.512us | 1 | 1 | 100.00 | |
| flash_ctrl_derr_detect | 93.830s | 6931.797us | 1 | 1 | 100.00 | |
| flash_ctrl_integrity | 332.510s | 9961.574us | 1 | 1 | 100.00 | |
| single_bit_err | 3 | 3 | 100.00 | |||
| flash_ctrl_read_word_sweep_serr | 8.190s | 27.850us | 1 | 1 | 100.00 | |
| flash_ctrl_ro_serr | 70.150s | 653.039us | 1 | 1 | 100.00 | |
| flash_ctrl_rw_serr | 108.680s | 8314.216us | 1 | 1 | 100.00 | |
| singlebit_err_counter | 1 | 1 | 100.00 | |||
| flash_ctrl_serr_counter | 57.510s | 6339.426us | 1 | 1 | 100.00 | |
| singlebit_err_address | 1 | 1 | 100.00 | |||
| flash_ctrl_serr_address | 32.050s | 2175.822us | 1 | 1 | 100.00 | |
| scramble | 5 | 5 | 100.00 | |||
| flash_ctrl_wo | 90.160s | 13561.327us | 1 | 1 | 100.00 | |
| flash_ctrl_write_word_sweep | 6.050s | 51.021us | 1 | 1 | 100.00 | |
| flash_ctrl_read_word_sweep | 5.460s | 88.894us | 1 | 1 | 100.00 | |
| flash_ctrl_ro | 59.080s | 2097.136us | 1 | 1 | 100.00 | |
| flash_ctrl_rw | 296.340s | 11190.743us | 1 | 1 | 100.00 | |
| filesystem_support | 1 | 1 | 100.00 | |||
| flash_ctrl_fs_sup | 19.150s | 686.777us | 1 | 1 | 100.00 | |
| rma_write_process_error | 2 | 2 | 100.00 | |||
| flash_ctrl_rma_err | 530.550s | 41096.972us | 1 | 1 | 100.00 | |
| flash_ctrl_hw_prog_rma_wipe_err | 176.380s | 10019.710us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| flash_ctrl_alert_test | 5.070s | 30.207us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| flash_ctrl_intr_test | 4.820s | 73.670us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| flash_ctrl_tl_errors | 7.880s | 191.715us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| flash_ctrl_tl_errors | 7.880s | 191.715us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| flash_ctrl_csr_hw_reset | 9.140s | 144.843us | 1 | 1 | 100.00 | |
| flash_ctrl_csr_rw | 5.640s | 237.914us | 1 | 1 | 100.00 | |
| flash_ctrl_csr_aliasing | 37.370s | 2652.059us | 1 | 1 | 100.00 | |
| flash_ctrl_same_csr_outstanding | 9.180s | 174.880us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| flash_ctrl_csr_hw_reset | 9.140s | 144.843us | 1 | 1 | 100.00 | |
| flash_ctrl_csr_rw | 5.640s | 237.914us | 1 | 1 | 100.00 | |
| flash_ctrl_csr_aliasing | 37.370s | 2652.059us | 1 | 1 | 100.00 | |
| flash_ctrl_same_csr_outstanding | 9.180s | 174.880us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| shadow_reg_update_error | 1 | 1 | 100.00 | |||
| flash_ctrl_shadow_reg_errors | 16.440s | 72.403us | 1 | 1 | 100.00 | |
| shadow_reg_read_clear_staged_value | 1 | 1 | 100.00 | |||
| flash_ctrl_shadow_reg_errors | 16.440s | 72.403us | 1 | 1 | 100.00 | |
| shadow_reg_storage_error | 1 | 1 | 100.00 | |||
| flash_ctrl_shadow_reg_errors | 16.440s | 72.403us | 1 | 1 | 100.00 | |
| shadowed_reset_glitch | 1 | 1 | 100.00 | |||
| flash_ctrl_shadow_reg_errors | 16.440s | 72.403us | 1 | 1 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 1 | 1 | 100.00 | |||
| flash_ctrl_shadow_reg_errors_with_csr_rw | 8.360s | 443.457us | 1 | 1 | 100.00 | |
| tl_intg_err | 2 | 2 | 100.00 | |||
| flash_ctrl_tl_intg_err | 331.230s | 1590.747us | 1 | 1 | 100.00 | |
| flash_ctrl_sec_cm | 1418.050s | 1927.538us | 1 | 1 | 100.00 | |
| sec_cm_reg_bus_integrity | 1 | 1 | 100.00 | |||
| flash_ctrl_tl_intg_err | 331.230s | 1590.747us | 1 | 1 | 100.00 | |
| sec_cm_host_bus_integrity | 1 | 1 | 100.00 | |||
| flash_ctrl_tl_intg_err | 331.230s | 1590.747us | 1 | 1 | 100.00 | |
| sec_cm_mem_bus_integrity | 2 | 2 | 100.00 | |||
| flash_ctrl_rd_intg | 13.020s | 216.477us | 1 | 1 | 100.00 | |
| flash_ctrl_wr_intg | 5.930s | 144.397us | 1 | 1 | 100.00 | |
| sec_cm_scramble_key_sideload | 1 | 1 | 100.00 | |||
| flash_ctrl_smoke | 61.280s | 87.781us | 1 | 1 | 100.00 | |
| sec_cm_lc_ctrl_intersig_mubi | 4 | 4 | 100.00 | |||
| flash_ctrl_otp_reset | 46.760s | 84.782us | 1 | 1 | 100.00 | |
| flash_ctrl_disable | 8.740s | 23.145us | 1 | 1 | 100.00 | |
| flash_ctrl_sec_info_access | 35.980s | 1590.634us | 1 | 1 | 100.00 | |
| flash_ctrl_connect | 6.360s | 31.961us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_config_regwen | 1 | 1 | 100.00 | |||
| flash_ctrl_config_regwen | 5.270s | 36.209us | 1 | 1 | 100.00 | |
| sec_cm_data_regions_config_regwen | 1 | 1 | 100.00 | |||
| flash_ctrl_csr_rw | 5.640s | 237.914us | 1 | 1 | 100.00 | |
| sec_cm_data_regions_config_shadow | 1 | 1 | 100.00 | |||
| flash_ctrl_shadow_reg_errors | 16.440s | 72.403us | 1 | 1 | 100.00 | |
| sec_cm_info_regions_config_regwen | 1 | 1 | 100.00 | |||
| flash_ctrl_csr_rw | 5.640s | 237.914us | 1 | 1 | 100.00 | |
| sec_cm_info_regions_config_shadow | 1 | 1 | 100.00 | |||
| flash_ctrl_shadow_reg_errors | 16.440s | 72.403us | 1 | 1 | 100.00 | |
| sec_cm_bank_config_regwen | 1 | 1 | 100.00 | |||
| flash_ctrl_csr_rw | 5.640s | 237.914us | 1 | 1 | 100.00 | |
| sec_cm_bank_config_shadow | 1 | 1 | 100.00 | |||
| flash_ctrl_shadow_reg_errors | 16.440s | 72.403us | 1 | 1 | 100.00 | |
| sec_cm_mem_ctrl_global_esc | 1 | 1 | 100.00 | |||
| flash_ctrl_disable | 8.740s | 23.145us | 1 | 1 | 100.00 | |
| sec_cm_mem_ctrl_local_esc | 2 | 2 | 100.00 | |||
| flash_ctrl_rd_intg | 13.020s | 216.477us | 1 | 1 | 100.00 | |
| flash_ctrl_access_after_disable | 5.240s | 22.125us | 1 | 1 | 100.00 | |
| sec_cm_mem_addr_infection | 1 | 1 | 100.00 | |||
| flash_ctrl_host_addr_infection | 12.100s | 55.569us | 1 | 1 | 100.00 | |
| sec_cm_mem_disable_config_mubi | 1 | 1 | 100.00 | |||
| flash_ctrl_disable | 8.740s | 23.145us | 1 | 1 | 100.00 | |
| sec_cm_exec_config_redun | 1 | 1 | 100.00 | |||
| flash_ctrl_fetch_code | 11.720s | 303.262us | 1 | 1 | 100.00 | |
| sec_cm_mem_scramble | 1 | 1 | 100.00 | |||
| flash_ctrl_rw | 296.340s | 11190.743us | 1 | 1 | 100.00 | |
| sec_cm_mem_integrity | 3 | 3 | 100.00 | |||
| flash_ctrl_rw_serr | 108.680s | 8314.216us | 1 | 1 | 100.00 | |
| flash_ctrl_rw_derr | 114.080s | 7720.512us | 1 | 1 | 100.00 | |
| flash_ctrl_integrity | 332.510s | 9961.574us | 1 | 1 | 100.00 | |
| sec_cm_rma_entry_mem_sec_wipe | 1 | 1 | 100.00 | |||
| flash_ctrl_hw_rma | 1501.790s | 195785.807us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_fsm_sparse | 1 | 1 | 100.00 | |||
| flash_ctrl_sec_cm | 1418.050s | 1927.538us | 1 | 1 | 100.00 | |
| sec_cm_phy_fsm_sparse | 1 | 1 | 100.00 | |||
| flash_ctrl_sec_cm | 1418.050s | 1927.538us | 1 | 1 | 100.00 | |
| sec_cm_phy_prog_fsm_sparse | 1 | 1 | 100.00 | |||
| flash_ctrl_sec_cm | 1418.050s | 1927.538us | 1 | 1 | 100.00 | |
| sec_cm_ctr_redun | 1 | 1 | 100.00 | |||
| flash_ctrl_sec_cm | 1418.050s | 1927.538us | 1 | 1 | 100.00 | |
| sec_cm_phy_arbiter_ctrl_redun | 1 | 1 | 100.00 | |||
| flash_ctrl_phy_arb_redun | 12.290s | 842.050us | 1 | 1 | 100.00 | |
| sec_cm_phy_host_grant_ctrl_consistency | 0 | 1 | 0.00 | |||
| flash_ctrl_phy_host_grant_err | 4.960s | 21.542us | 0 | 1 | 0.00 | |
| sec_cm_phy_ack_ctrl_consistency | 1 | 1 | 100.00 | |||
| flash_ctrl_phy_ack_consistency | 5.190s | 56.694us | 1 | 1 | 100.00 | |
| sec_cm_fifo_ctr_redun | 1 | 1 | 100.00 | |||
| flash_ctrl_sec_cm | 1418.050s | 1927.538us | 1 | 1 | 100.00 | |
| sec_cm_mem_tl_lc_gate_fsm_sparse | 1 | 1 | 100.00 | |||
| flash_ctrl_sec_cm | 1418.050s | 1927.538us | 1 | 1 | 100.00 | |
| sec_cm_prog_tl_lc_gate_fsm_sparse | 1 | 1 | 100.00 | |||
| flash_ctrl_sec_cm | 1418.050s | 1927.538us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| asymmetric_read_path | 1 | 1 | 100.00 | |||
| flash_ctrl_rd_ooo | 17.800s | 80.118us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 1 | 1 | 100.00 | |||
| flash_ctrl_basic_rw | 137.370s | 864.574us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job timed out after * minutes | ||||
| flash_ctrl_intr_wr_slow_flash | 31549525004224222759208299012378384453324261653128737461556885718482562838906 | None |
Job timed out after 60 minutes
|
|
| Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))' | ||||
| flash_ctrl_phy_host_grant_err | 79448312729527834868967309887334344649990577911330144754227966996172130579220 | 130 |
Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))'
UVM_ERROR @ 21541.9 ns: (alert_esc_if.sv:202) [ASSERT FAILED] AlertKnown_A
UVM_INFO @ 21541.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|