Simulation Results: hmac

 
08/04/2026 18:06:49 DVSim: v1.17.3 sha: 007b0cf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 78.80 %
  • code
  • 97.20 %
  • assert
  • 96.70 %
  • func
  • 42.51 %
  • line
  • 99.74 %
  • branch
  • 99.17 %
  • cond
  • 95.90 %
  • toggle
  • 100.00 %
  • FSM
  • 91.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 4.620s 387.575us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.660s 19.068us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.630s 16.478us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 10.330s 5495.470us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 2.060s 114.732us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 525.590s 80698.292us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.630s 16.478us 1 1 100.00
hmac_csr_aliasing 2.060s 114.732us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 30.910s 9479.203us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 26.780s 630.560us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 181.270s 6272.429us 1 1 100.00
hmac_test_sha384_vectors 284.270s 30923.412us 1 1 100.00
hmac_test_sha512_vectors 17.430s 218.207us 1 1 100.00
hmac_test_hmac256_vectors 8.030s 411.813us 1 1 100.00
hmac_test_hmac384_vectors 8.220s 316.990us 1 1 100.00
hmac_test_hmac512_vectors 9.960s 1068.168us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 0.610s 16.439us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 10.420s 4196.435us 1 1 100.00
error 1 1 100.00
hmac_error 46.160s 21789.737us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 54.450s 4640.625us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 4.620s 387.575us 1 1 100.00
hmac_long_msg 30.910s 9479.203us 1 1 100.00
hmac_back_pressure 26.780s 630.560us 1 1 100.00
hmac_datapath_stress 10.420s 4196.435us 1 1 100.00
hmac_burst_wr 0.610s 16.439us 1 1 100.00
hmac_stress_all 13.690s 787.695us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 4.620s 387.575us 1 1 100.00
hmac_long_msg 30.910s 9479.203us 1 1 100.00
hmac_back_pressure 26.780s 630.560us 1 1 100.00
hmac_datapath_stress 10.420s 4196.435us 1 1 100.00
hmac_wipe_secret 54.450s 4640.625us 1 1 100.00
hmac_test_sha256_vectors 181.270s 6272.429us 1 1 100.00
hmac_test_sha384_vectors 284.270s 30923.412us 1 1 100.00
hmac_test_sha512_vectors 17.430s 218.207us 1 1 100.00
hmac_test_hmac256_vectors 8.030s 411.813us 1 1 100.00
hmac_test_hmac384_vectors 8.220s 316.990us 1 1 100.00
hmac_test_hmac512_vectors 9.960s 1068.168us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 4.620s 387.575us 1 1 100.00
hmac_long_msg 30.910s 9479.203us 1 1 100.00
hmac_back_pressure 26.780s 630.560us 1 1 100.00
hmac_datapath_stress 10.420s 4196.435us 1 1 100.00
hmac_burst_wr 0.610s 16.439us 1 1 100.00
hmac_error 46.160s 21789.737us 1 1 100.00
hmac_wipe_secret 54.450s 4640.625us 1 1 100.00
hmac_test_sha256_vectors 181.270s 6272.429us 1 1 100.00
hmac_test_sha384_vectors 284.270s 30923.412us 1 1 100.00
hmac_test_sha512_vectors 17.430s 218.207us 1 1 100.00
hmac_test_hmac256_vectors 8.030s 411.813us 1 1 100.00
hmac_test_hmac384_vectors 8.220s 316.990us 1 1 100.00
hmac_test_hmac512_vectors 9.960s 1068.168us 1 1 100.00
hmac_stress_all 13.690s 787.695us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 13.690s 787.695us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.530s 31.775us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.560s 38.855us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 1.830s 513.041us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 1.830s 513.041us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.660s 19.068us 1 1 100.00
hmac_csr_rw 0.630s 16.478us 1 1 100.00
hmac_csr_aliasing 2.060s 114.732us 1 1 100.00
hmac_same_csr_outstanding 1.360s 85.015us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.660s 19.068us 1 1 100.00
hmac_csr_rw 0.630s 16.478us 1 1 100.00
hmac_csr_aliasing 2.060s 114.732us 1 1 100.00
hmac_same_csr_outstanding 1.360s 85.015us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.690s 70.484us 1 1 100.00
hmac_tl_intg_err 2.150s 155.490us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.150s 155.490us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 4.620s 387.575us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 0.800s 27.836us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 8.840s 1599.986us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 0.750s 18.092us 1 1 100.00