Simulation Results

Simulation Results: i2c

08/04/2026 18:06:49 DVSim: v1.17.3 sha: 007b0cf json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
86.37 %

code
81.41 %

assert
96.19 %

func
81.50 %

line
96.35 %

branch
92.12 %

cond
84.86 %

toggle
89.66 %

FSM
44.05 %

Validation stages

V1		100.00%
V2		90.24%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	18.660s	8073.283us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	4.180s	513.904us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.690s	26.136us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.630s	37.910us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	1.910s	194.651us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.310s	78.430us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	1.180s	114.066us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.630s	37.910us	1	1	100.00
	i2c_csr_aliasing	1.310s	78.430us	1	1	100.00

37/41 passed

90.24 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	2.550s	334.350us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	1177.780s	84363.052us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	20.540s	3183.752us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.640s	145.880us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	185.740s	21549.294us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	54.220s	5733.362us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	0.810s	182.139us	1	1	100.00
	i2c_host_fifo_fmt_empty	8.090s	665.800us	1	1	100.00
	i2c_host_fifo_reset_rx	2.310s	605.828us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	28.190s	1750.020us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	15.890s	592.698us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	0.580s	44.099us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	1.690s	1877.045us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	15.870s	25992.677us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	3.180s	1379.267us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	34.400s	1883.817us	1	1	100.00
	i2c_target_intr_smoke	3.470s	1886.707us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	0.700s	181.063us	1	1	100.00
	i2c_target_fifo_reset_tx	0.790s	338.882us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	86.340s	32348.797us	1	1	100.00
	i2c_target_stress_rd	34.400s	1883.817us	1	1	100.00
	i2c_target_intr_stress_wr	0.980s	219.218us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	3.910s	4519.199us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	7.890s	2974.897us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	2.970s	1066.712us	1	1	100.00
target_mode_glitch				1	1	100.00
	i2c_target_hrst	1.480s	679.802us	1	1	100.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	1.440s	829.481us	1	1	100.00
	i2c_target_fifo_watermarks_tx	1.190s	171.557us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	20.540s	3183.752us	1	1	100.00
	i2c_host_perf_precise	0.780s	57.478us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	15.890s	592.698us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	1.770s	121.649us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	1.860s	8354.717us	1	1	100.00
	i2c_target_nack_acqfull_addr	1.500s	463.157us	1	1	100.00
	i2c_target_nack_txstretch	1.120s	122.018us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	3.780s	1836.362us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.590s	2048.204us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.620s	19.711us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.650s	31.223us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	1.870s	549.877us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	1.870s	549.877us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.690s	26.136us	1	1	100.00
	i2c_csr_rw	0.630s	37.910us	1	1	100.00
	i2c_csr_aliasing	1.310s	78.430us	1	1	100.00
	i2c_same_csr_outstanding	0.940s	64.663us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.690s	26.136us	1	1	100.00
	i2c_csr_rw	0.630s	37.910us	1	1	100.00
	i2c_csr_aliasing	1.310s	78.430us	1	1	100.00
	i2c_same_csr_outstanding	0.940s	64.663us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_sec_cm	0.840s	122.132us	1	1	100.00
	i2c_tl_intg_err	1.100s	267.427us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.100s	267.427us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	4.740s	1518.326us	1
target_error_intr				1
	i2c_target_unexp_stop	1.090s	153.586us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	7.690s	1522.901us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
	i2c_host_error_intr	53874567306555538843063221128289863560894098675936417783878064178701831736502	91	UVM_ERROR @ 334349646 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between UVM_INFO @ 334349646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	85748281950275074207860678607585350123201345855002324800277612071785591534620	183	UVM_ERROR @ 84363052344 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between UVM_INFO @ 84363052344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	20522192641346871875016849816325760608139839195965570194931378253489288697668	118	UVM_ERROR @ 1522900852 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between UVM_INFO @ 1522900852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
	i2c_target_glitch	87671258248689751284938556031249078587131250418747610524459786798001550724917	89	UVM_ERROR @ 1877045039 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between UVM_INFO @ 1877045039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])
	i2c_target_unexp_stop	87714590889906168080940137763953761597585420012036878540020463447873639409556	83	UVM_ERROR @ 153586161 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 149 [0x95]) UVM_INFO @ 153586161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
	i2c_host_stress_all_with_rand_reset	78765451203206905824315754395283023454815482044523825895031408249188603855138	89	UVM_ERROR @ 1518325761 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 1518325761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=, Comparison=CompareOpEq, exp_data=, call_count=3)
	i2c_host_mode_toggle	108892047998054207271015108939264653607761372764300418371643293640196155784444	84	UVM_FATAL @ 44099491 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=0x61ee494, Comparison=CompareOpEq, exp_data=0x1, call_count=3) UVM_INFO @ 44099491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---