Simulation Results: kmac/masked

 
08/04/2026 18:06:49 DVSim: v1.17.3 sha: 007b0cf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.16 %
  • code
  • 90.51 %
  • assert
  • 97.84 %
  • func
  • 94.13 %
  • line
  • 98.91 %
  • branch
  • 96.30 %
  • cond
  • 90.93 %
  • toggle
  • 99.51 %
  • FSM
  • 66.90 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 27.450s 5112.663us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 0.810s 68.229us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 0.940s 31.979us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 9.810s 2799.356us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 6.170s 682.547us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 1.320s 138.510us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 0.940s 31.979us 1 1 100.00
kmac_csr_aliasing 6.170s 682.547us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.640s 27.749us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.320s 41.936us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 2469.680s 28468.921us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 207.090s 7180.225us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 30.280s 8094.599us 1 1 100.00
kmac_test_vectors_sha3_256 34.070s 4352.202us 1 1 100.00
kmac_test_vectors_sha3_384 1093.350s 120326.735us 1 1 100.00
kmac_test_vectors_sha3_512 11.820s 953.252us 1 1 100.00
kmac_test_vectors_shake_128 2204.210s 301237.820us 1 1 100.00
kmac_test_vectors_shake_256 99.810s 28442.760us 1 1 100.00
kmac_test_vectors_kmac 1.810s 390.244us 1 1 100.00
kmac_test_vectors_kmac_xof 2.480s 1033.378us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 260.670s 13494.762us 1 1 100.00
app 1 1 100.00
kmac_app 80.560s 6301.417us 1 1 100.00
app_with_partial_data 1 1 100.00
kmac_app_with_partial_data 170.610s 5499.781us 1 1 100.00
entropy_refresh 1 1 100.00
kmac_entropy_refresh 56.160s 7483.954us 1 1 100.00
error 1 1 100.00
kmac_error 27.700s 517.689us 1 1 100.00
key_error 1 1 100.00
kmac_key_error 7.440s 3070.031us 1 1 100.00
sideload_invalid 1 1 100.00
kmac_sideload_invalid 2.640s 93.719us 1 1 100.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 0.940s 94.100us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 0.890s 128.213us 1 1 100.00
entropy_ready_error 1 1 100.00
kmac_entropy_ready_error 33.660s 5602.968us 1 1 100.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.190s 427.627us 1 1 100.00
stress_all 1 1 100.00
kmac_stress_all 235.640s 46205.206us 1 1 100.00
intr_test 1 1 100.00
kmac_intr_test 0.740s 16.353us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 0.740s 40.954us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 1.760s 66.280us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 1.760s 66.280us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 0.810s 68.229us 1 1 100.00
kmac_csr_rw 0.940s 31.979us 1 1 100.00
kmac_csr_aliasing 6.170s 682.547us 1 1 100.00
kmac_same_csr_outstanding 1.280s 61.276us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 0.810s 68.229us 1 1 100.00
kmac_csr_rw 0.940s 31.979us 1 1 100.00
kmac_csr_aliasing 6.170s 682.547us 1 1 100.00
kmac_same_csr_outstanding 1.280s 61.276us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.180s 43.605us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.180s 43.605us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.180s 43.605us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.180s 43.605us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 3.360s 378.662us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_tl_intg_err 2.840s 1067.961us 1 1 100.00
kmac_sec_cm 25.330s 29253.795us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 2.840s 1067.961us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.190s 427.627us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 27.450s 5112.663us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 260.670s 13494.762us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.180s 43.605us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 25.330s 29253.795us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 25.330s 29253.795us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 25.330s 29253.795us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 27.450s 5112.663us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.190s 427.627us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 25.330s 29253.795us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 1 1 100.00
kmac_mubi 64.690s 16578.300us 1 1 100.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 27.450s 5112.663us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
kmac_stress_all_with_rand_reset 122.990s 2496.441us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:847) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*])
kmac_stress_all_with_rand_reset 5695749286989818143109795250427069298790357476042753178576846030151459330191 282
UVM_ERROR @ 2496440716 ps: (cip_base_vseq.sv:847) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 2496440716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---