Simulation Results: lc_ctrl/volatile_unlock_disabled

 
08/04/2026 18:06:49 DVSim: v1.17.3 sha: 007b0cf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.17 %
  • code
  • 83.85 %
  • assert
  • 94.13 %
  • func
  • 92.53 %
  • line
  • 97.12 %
  • branch
  • 93.67 %
  • cond
  • 79.52 %
  • toggle
  • 86.31 %
  • FSM
  • 62.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.000s 63.831us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.770s 22.072us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.730s 16.691us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.160s 76.879us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.980s 22.479us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.900s 46.384us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.730s 16.691us 1 1 100.00
lc_ctrl_csr_aliasing 0.980s 22.479us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.130s 259.242us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 6.960s 331.556us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.700s 14.725us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.580s 38.292us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 5.990s 327.489us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 6.810s 1190.419us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 5.990s 327.489us 1 1 100.00
lc_ctrl_prog_failure 1.580s 38.292us 1 1 100.00
lc_ctrl_errors 6.810s 1190.419us 1 1 100.00
lc_ctrl_security_escalation 6.140s 309.537us 1 1 100.00
lc_ctrl_jtag_state_failure 31.280s 3390.144us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.460s 412.763us 1 1 100.00
lc_ctrl_jtag_errors 28.800s 12582.741us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 2.260s 289.731us 1 1 100.00
lc_ctrl_jtag_state_post_trans 7.890s 1174.917us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.460s 412.763us 1 1 100.00
lc_ctrl_jtag_errors 28.800s 12582.741us 1 1 100.00
lc_ctrl_jtag_access 5.710s 633.731us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 12.240s 6233.771us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.140s 361.443us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.080s 322.437us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 4.860s 3153.209us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 8.340s 602.648us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 0.920s 53.095us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.840s 441.739us 1 1 100.00
lc_ctrl_jtag_alert_test 0.720s 149.679us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 26.240s 1817.849us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.810s 23.557us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 52.630s 29250.299us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.800s 28.160us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.840s 45.923us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.840s 45.923us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.770s 22.072us 1 1 100.00
lc_ctrl_csr_rw 0.730s 16.691us 1 1 100.00
lc_ctrl_csr_aliasing 0.980s 22.479us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.910s 21.939us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.770s 22.072us 1 1 100.00
lc_ctrl_csr_rw 0.730s 16.691us 1 1 100.00
lc_ctrl_csr_aliasing 0.980s 22.479us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.910s 21.939us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.430s 120.455us 1 1 100.00
lc_ctrl_tl_intg_err 1.640s 69.132us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.640s 69.132us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 6.960s 331.556us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 5.990s 327.489us 1 1 100.00
lc_ctrl_sec_cm 5.430s 120.455us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 5.990s 327.489us 1 1 100.00
lc_ctrl_sec_cm 5.430s 120.455us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 5.990s 327.489us 1 1 100.00
lc_ctrl_sec_cm 5.430s 120.455us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 5.990s 327.489us 1 1 100.00
lc_ctrl_sec_cm 5.430s 120.455us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 5.990s 327.489us 1 1 100.00
lc_ctrl_sec_cm 5.430s 120.455us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 5.990s 327.489us 1 1 100.00
lc_ctrl_sec_cm 5.430s 120.455us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 5.990s 327.489us 1 1 100.00
lc_ctrl_sec_cm 5.430s 120.455us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 5.990s 327.489us 1 1 100.00
lc_ctrl_sec_cm 5.430s 120.455us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.140s 309.537us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.130s 259.242us 1 1 100.00
lc_ctrl_jtag_state_post_trans 7.890s 1174.917us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.820s 279.828us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.820s 279.828us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.470s 386.158us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.320s 1226.180us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.320s 1226.180us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 50.300s 1957.956us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
lc_ctrl_stress_all_with_rand_reset 35637129676573295206258588686164556406156982389966962161656279213429878748522 3735
UVM_ERROR @ 1957956115 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
UVM_INFO @ 1957956115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---