Simulation Results: lc_ctrl/volatile_unlock_enabled

 
08/04/2026 18:06:49 DVSim: v1.17.3 sha: 007b0cf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.91 %
  • code
  • 83.62 %
  • assert
  • 94.13 %
  • func
  • 91.99 %
  • line
  • 96.93 %
  • branch
  • 93.03 %
  • cond
  • 79.07 %
  • toggle
  • 87.37 %
  • FSM
  • 61.68 %
Validation stages
V1
100.00%
V2
93.33%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.080s 59.236us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.720s 124.687us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.970s 23.751us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.000s 65.143us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.940s 231.303us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.800s 30.990us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.970s 23.751us 1 1 100.00
lc_ctrl_csr_aliasing 0.940s 231.303us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.580s 102.832us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 7.750s 192.611us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.790s 13.676us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.440s 285.608us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 6.470s 2278.471us 1 1 100.00
lc_errors 0 1 0.00
lc_ctrl_errors 2.540s 605.472us 0 1 0.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 6.470s 2278.471us 1 1 100.00
lc_ctrl_prog_failure 1.440s 285.608us 1 1 100.00
lc_ctrl_errors 2.540s 605.472us 0 1 0.00
lc_ctrl_security_escalation 5.540s 534.584us 1 1 100.00
lc_ctrl_jtag_state_failure 11.700s 5037.029us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.310s 602.928us 1 1 100.00
lc_ctrl_jtag_errors 13.640s 1595.529us 0 1 0.00
jtag_access 12 13 92.31
lc_ctrl_jtag_csr_hw_reset 1.160s 80.112us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.030s 206.794us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 7.800s 2251.380us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.520s 1808.327us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 0.840s 58.780us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.490s 366.020us 1 1 100.00
lc_ctrl_jtag_alert_test 1.260s 47.950us 1 1 100.00
lc_ctrl_jtag_smoke 4.590s 597.804us 1 1 100.00
lc_ctrl_jtag_state_post_trans 12.710s 690.600us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.310s 602.928us 1 1 100.00
lc_ctrl_jtag_errors 13.640s 1595.529us 0 1 0.00
lc_ctrl_jtag_access 3.130s 312.117us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 9.530s 1103.548us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 2.880s 481.288us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.740s 39.107us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 130.010s 25280.175us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.700s 16.310us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.560s 69.355us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.560s 69.355us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.720s 124.687us 1 1 100.00
lc_ctrl_csr_rw 0.970s 23.751us 1 1 100.00
lc_ctrl_csr_aliasing 0.940s 231.303us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.880s 27.734us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.720s 124.687us 1 1 100.00
lc_ctrl_csr_rw 0.970s 23.751us 1 1 100.00
lc_ctrl_csr_aliasing 0.940s 231.303us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.880s 27.734us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_tl_intg_err 1.990s 84.755us 1 1 100.00
lc_ctrl_sec_cm 5.710s 1112.196us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.990s 84.755us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 7.750s 192.611us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 6.470s 2278.471us 1 1 100.00
lc_ctrl_sec_cm 5.710s 1112.196us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 6.470s 2278.471us 1 1 100.00
lc_ctrl_sec_cm 5.710s 1112.196us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.470s 2278.471us 1 1 100.00
lc_ctrl_sec_cm 5.710s 1112.196us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.470s 2278.471us 1 1 100.00
lc_ctrl_sec_cm 5.710s 1112.196us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 6.470s 2278.471us 1 1 100.00
lc_ctrl_sec_cm 5.710s 1112.196us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.470s 2278.471us 1 1 100.00
lc_ctrl_sec_cm 5.710s 1112.196us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.470s 2278.471us 1 1 100.00
lc_ctrl_sec_cm 5.710s 1112.196us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 6.470s 2278.471us 1 1 100.00
lc_ctrl_sec_cm 5.710s 1112.196us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.540s 534.584us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.580s 102.832us 1 1 100.00
lc_ctrl_jtag_state_post_trans 12.710s 690.600us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.010s 334.627us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.010s 334.627us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.970s 251.704us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.790s 273.236us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.790s 273.236us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 12.720s 739.478us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*])
lc_ctrl_errors 5943412965504572834751581693921830850837599664890943658326900699600117661111 1629
UVM_ERROR @ 605472278 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 605472278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_errors 99506761515415895331310172227854744354855426956250052706468143298071273013874 3823
UVM_ERROR @ 1595528938 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1595528938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---