Simulation Results: otp_ctrl

 
08/04/2026 18:06:49 DVSim: v1.17.3 sha: 007b0cf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 80.20 %
  • code
  • 77.75 %
  • assert
  • 93.86 %
  • func
  • 68.99 %
  • line
  • 88.67 %
  • branch
  • 83.17 %
  • cond
  • 89.66 %
  • toggle
  • 81.95 %
  • FSM
  • 45.31 %
Validation stages
V1
100.00%
V2
90.00%
V2S
88.89%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.300s 50.355us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 4.920s 861.041us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 1.760s 202.859us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.200s 531.510us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 6.750s 999.402us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 2.760s 382.828us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 1.450s 136.259us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.200s 531.510us 1 1 100.00
otp_ctrl_csr_aliasing 2.760s 382.828us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.030s 122.742us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.070s 79.788us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 16.920s 12811.348us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 2.490s 105.886us 1 1 100.00
partition_check 1 2 50.00
otp_ctrl_background_chks 11.850s 745.321us 1 1 100.00
otp_ctrl_check_fail 3.570s 3601.798us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 5.940s 569.280us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 10.640s 4668.614us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 9.080s 329.988us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 11.530s 1342.287us 1 1 100.00
otp_ctrl_parallel_lc_esc 5.150s 171.363us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 9.870s 1939.539us 1 1 100.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 6.050s 4784.796us 1 1 100.00
test_access 1 1 100.00
otp_ctrl_test_access 13.810s 10025.185us 1 1 100.00
stress_all 0 1 0.00
otp_ctrl_stress_all 67.580s 63926.414us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.020s 39.559us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.180s 85.312us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 2.380s 228.205us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 2.380s 228.205us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.760s 202.859us 1 1 100.00
otp_ctrl_csr_rw 1.200s 531.510us 1 1 100.00
otp_ctrl_csr_aliasing 2.760s 382.828us 1 1 100.00
otp_ctrl_same_csr_outstanding 1.640s 121.581us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.760s 202.859us 1 1 100.00
otp_ctrl_csr_rw 1.200s 531.510us 1 1 100.00
otp_ctrl_csr_aliasing 2.760s 382.828us 1 1 100.00
otp_ctrl_same_csr_outstanding 1.640s 121.581us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 90.010s 15544.465us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_tl_intg_err 6.060s 635.493us 1 1 100.00
otp_ctrl_sec_cm 90.010s 15544.465us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 90.010s 15544.465us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 90.010s 15544.465us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 6.060s 635.493us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 4.920s 861.041us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 4.920s 861.041us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 90.010s 15544.465us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 90.010s 15544.465us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 90.010s 15544.465us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 90.010s 15544.465us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 90.010s 15544.465us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 90.010s 15544.465us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 90.010s 15544.465us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 90.010s 15544.465us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 90.010s 15544.465us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 90.010s 15544.465us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 90.010s 15544.465us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 90.010s 15544.465us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 90.010s 15544.465us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 90.010s 15544.465us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 90.010s 15544.465us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 5.150s 171.363us 1 1 100.00
otp_ctrl_sec_cm 90.010s 15544.465us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 5.150s 171.363us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 5.150s 171.363us 1 1 100.00
sec_cm_part_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 5.150s 171.363us 1 1 100.00
otp_ctrl_macro_errs 6.050s 4784.796us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 5.150s 171.363us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 5.150s 171.363us 1 1 100.00
otp_ctrl_sec_cm 90.010s 15544.465us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 5.150s 171.363us 1 1 100.00
otp_ctrl_sec_cm 90.010s 15544.465us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 5.150s 171.363us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 5.150s 171.363us 1 1 100.00
sec_cm_part_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 5.150s 171.363us 1 1 100.00
otp_ctrl_macro_errs 6.050s 4784.796us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 5.150s 171.363us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 5.150s 171.363us 1 1 100.00
otp_ctrl_sec_cm 90.010s 15544.465us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 2.490s 105.886us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 3.570s 3601.798us 0 1 0.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 10.640s 4668.614us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 10.640s 4668.614us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 10.640s 4668.614us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 10.640s 4668.614us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 10.640s 4668.614us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 4.920s 861.041us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 10.640s 4668.614us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 4.920s 861.041us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 90.010s 15544.465us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 5.940s 569.280us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 4.920s 861.041us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 4.920s 861.041us 1 1 100.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 6.050s 4784.796us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 9.170s 5979.246us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 1.100s 26.810us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_*
otp_ctrl_check_fail 49819592108645022145047171989942190536222196447649347405812560096085465060345 2303
UVM_ERROR @ 3601798154 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2514892418 [0x95e63682] vs 2514888322 [0x95e62682]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 3601798154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = *
otp_ctrl_stress_all_with_rand_reset 98206485474295650394512269177679661779042841962452886384089410118485155100856 100
UVM_ERROR @ 26810025 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 26810025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1315) [otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_check_error does not trigger!
otp_ctrl_stress_all 45714752764653526753728680268621978486926225528226529604549753445346675530364 42832
UVM_ERROR @ 63926413809 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 63926413809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---