Simulation Results: pattgen

 
08/04/2026 18:06:49 DVSim: v1.17.3 sha: 007b0cf json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.08 %
  • code
  • 98.87 %
  • assert
  • 96.95 %
  • func
  • 89.42 %
  • block
  • 100.00 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • toggle
  • 96.61 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pattgen_smoke 1.000s 56.784us 1 1 100.00
csr_hw_reset 1 1 100.00
pattgen_csr_hw_reset 1.000s 15.330us 1 1 100.00
csr_rw 1 1 100.00
pattgen_csr_rw 1.000s 12.577us 1 1 100.00
csr_bit_bash 1 1 100.00
pattgen_csr_bit_bash 2.000s 944.642us 1 1 100.00
csr_aliasing 1 1 100.00
pattgen_csr_aliasing 1.000s 39.885us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pattgen_csr_mem_rw_with_rand_reset 1.000s 17.446us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pattgen_csr_rw 1.000s 12.577us 1 1 100.00
pattgen_csr_aliasing 1.000s 39.885us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
perf 0 1 0.00
pattgen_perf 3112.000s 600000.000us 0 1 0.00
cnt_rollover 1 1 100.00
cnt_rollover 31.000s 8782.893us 1 1 100.00
error 1 1 100.00
pattgen_error 1.000s 43.359us 1 1 100.00
stress_all 1 1 100.00
pattgen_stress_all 6761.000s 5463432.171us 1 1 100.00
alert_test 1 1 100.00
pattgen_alert_test 1.000s 70.156us 1 1 100.00
intr_test 1 1 100.00
pattgen_intr_test 1.000s 12.073us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pattgen_tl_errors 2.000s 125.984us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pattgen_tl_errors 2.000s 125.984us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 15.330us 1 1 100.00
pattgen_csr_rw 1.000s 12.577us 1 1 100.00
pattgen_csr_aliasing 1.000s 39.885us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 59.015us 1 1 100.00
tl_d_partial_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 15.330us 1 1 100.00
pattgen_csr_rw 1.000s 12.577us 1 1 100.00
pattgen_csr_aliasing 1.000s 39.885us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 59.015us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pattgen_sec_cm 1.000s 76.279us 1 1 100.00
pattgen_tl_intg_err 1.000s 162.949us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pattgen_tl_intg_err 1.000s 162.949us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
pattgen_stress_all_with_rand_reset 16.000s 13402.753us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
pattgen_inactive_level 2.000s 20.436us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
pattgen_perf 106149303335746416832457445956332592805473585863439673622522196414694021379510 99
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (pattgen_scoreboard.sv:263) scoreboard [scoreboard]
pattgen_stress_all_with_rand_reset 60077951351085869398126200249348435242274713663974763357720753373921724721534 131
UVM_ERROR @ 1004653420 ps: (pattgen_scoreboard.sv:263) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
--> channel 1 item mismatch!
--> EXP:
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Name Type Size Value