Simulation Results: pwrmgr

 
08/04/2026 18:06:49 DVSim: v1.17.3 sha: 007b0cf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.82 %
  • code
  • 94.41 %
  • assert
  • 96.34 %
  • func
  • 96.71 %
  • line
  • 98.92 %
  • branch
  • 95.61 %
  • cond
  • 93.49 %
  • toggle
  • 90.02 %
  • FSM
  • 94.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.620s 39.544us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.610s 38.026us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.600s 53.003us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.930s 821.217us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.670s 27.858us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.660s 57.893us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.600s 53.003us 1 1 100.00
pwrmgr_csr_aliasing 0.670s 27.858us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.680s 102.198us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.680s 102.198us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.670s 33.359us 1 1 100.00
pwrmgr_lowpower_invalid 0.640s 49.827us 1 1 100.00
reset 2 2 100.00
pwrmgr_reset 0.680s 55.384us 1 1 100.00
pwrmgr_reset_invalid 0.640s 162.123us 1 1 100.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.680s 55.384us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.730s 352.232us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.620s 48.422us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.590s 84.231us 1 1 100.00
stress_all 1 1 100.00
pwrmgr_stress_all 1.060s 194.965us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.580s 18.898us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.280s 77.993us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.280s 77.993us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.610s 38.026us 1 1 100.00
pwrmgr_csr_rw 0.600s 53.003us 1 1 100.00
pwrmgr_csr_aliasing 0.670s 27.858us 1 1 100.00
pwrmgr_same_csr_outstanding 0.780s 69.875us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.610s 38.026us 1 1 100.00
pwrmgr_csr_rw 0.600s 53.003us 1 1 100.00
pwrmgr_csr_aliasing 0.670s 27.858us 1 1 100.00
pwrmgr_same_csr_outstanding 0.780s 69.875us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
pwrmgr_sec_cm 0.660s 18.024us 0 1 0.00
pwrmgr_tl_intg_err 0.590s 8.211us 0 1 0.00
prim_count_check 0 1 0.00
pwrmgr_sec_cm 0.660s 18.024us 0 1 0.00
prim_fsm_check 0 1 0.00
pwrmgr_sec_cm 0.660s 18.024us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
pwrmgr_tl_intg_err 0.590s 8.211us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.760s 817.792us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 1 1 100.00
pwrmgr_wakeup_reset 0.730s 352.232us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.710s 164.778us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.560s 32.922us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 0 1 0.00
pwrmgr_sec_cm 0.660s 18.024us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
pwrmgr_sec_cm 0.660s 18.024us 0 1 0.00
sec_cm_fsm_terminal 0 1 0.00
pwrmgr_sec_cm 0.660s 18.024us 0 1 0.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.570s 72.349us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.610s 45.348us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.660s 150.012us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.600s 53.003us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.600s 53.003us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 1 1 100.00
pwrmgr_escalation_timeout 0.680s 157.830us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 2.840s 2212.369us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [pwrmgr_common_vseq] expect alert:fatal_fault to fire
pwrmgr_sec_cm 53110631554523886105221515120881398743613420655927451231875813582595400002418 84
UVM_ERROR @ 18024284 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] expect alert:fatal_fault to fire
UVM_INFO @ 18024284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_tl_intg_err 7771453156659355689717916497151251340551373225031187522265261303893087960955 87
UVM_ERROR @ 8210578 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] expect alert:fatal_fault to fire
UVM_INFO @ 8210578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---