Simulation Results: rom_ctrl/32kb

 
08/04/2026 18:06:49 DVSim: v1.17.3 sha: 007b0cf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.26 %
  • code
  • 96.05 %
  • assert
  • 96.80 %
  • func
  • 95.94 %
  • line
  • 99.32 %
  • branch
  • 98.18 %
  • cond
  • 96.73 %
  • toggle
  • 99.34 %
  • FSM
  • 86.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 3.880s 139.421us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 4.900s 568.582us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 2.790s 374.584us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.000s 213.376us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.190s 1277.902us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.360s 324.039us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 2.790s 374.584us 1 1 100.00
rom_ctrl_csr_aliasing 3.190s 1277.902us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.180s 554.745us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 2.750s 417.448us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 3.270s 399.171us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 11.070s 854.603us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 5.470s 2123.648us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 2.830s 385.608us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 5.030s 166.052us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 5.030s 166.052us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.900s 568.582us 1 1 100.00
rom_ctrl_csr_rw 2.790s 374.584us 1 1 100.00
rom_ctrl_csr_aliasing 3.190s 1277.902us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.540s 242.960us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.900s 568.582us 1 1 100.00
rom_ctrl_csr_rw 2.790s 374.584us 1 1 100.00
rom_ctrl_csr_aliasing 3.190s 1277.902us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.540s 242.960us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 66.330s 3605.851us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 15.020s 2176.202us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 173.540s 972.662us 1 1 100.00
rom_ctrl_tl_intg_err 21.110s 398.249us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 173.540s 972.662us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 173.540s 972.662us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 66.330s 3605.851us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 66.330s 3605.851us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 66.330s 3605.851us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 66.330s 3605.851us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 66.330s 3605.851us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 173.540s 972.662us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 173.540s 972.662us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 3.880s 139.421us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 3.880s 139.421us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 3.880s 139.421us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 21.110s 398.249us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 66.330s 3605.851us 1 1 100.00
rom_ctrl_kmac_err_chk 5.470s 2123.648us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 66.330s 3605.851us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 66.330s 3605.851us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 66.330s 3605.851us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 15.020s 2176.202us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 173.540s 972.662us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 37.370s 3491.591us 1 1 100.00