Simulation Results: rom_ctrl/64kb

 
08/04/2026 18:06:49 DVSim: v1.17.3 sha: 007b0cf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.52 %
  • code
  • 98.14 %
  • assert
  • 96.80 %
  • func
  • 97.61 %
  • line
  • 99.59 %
  • branch
  • 99.27 %
  • cond
  • 98.51 %
  • toggle
  • 100.00 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 6.770s 225.660us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 8.640s 301.085us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 6.130s 706.514us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 6.340s 579.821us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 5.440s 205.788us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 5.290s 970.120us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 6.130s 706.514us 1 1 100.00
rom_ctrl_csr_aliasing 5.440s 205.788us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 5.610s 220.474us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 5.530s 236.916us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 6.560s 220.575us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 24.260s 756.726us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 10.990s 817.556us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 6.660s 288.277us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 7.680s 992.048us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 7.680s 992.048us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 8.640s 301.085us 1 1 100.00
rom_ctrl_csr_rw 6.130s 706.514us 1 1 100.00
rom_ctrl_csr_aliasing 5.440s 205.788us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.200s 1070.103us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 8.640s 301.085us 1 1 100.00
rom_ctrl_csr_rw 6.130s 706.514us 1 1 100.00
rom_ctrl_csr_aliasing 5.440s 205.788us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.200s 1070.103us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 102.950s 14277.945us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 36.280s 3758.761us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 207.900s 713.849us 1 1 100.00
rom_ctrl_tl_intg_err 88.180s 7326.458us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 207.900s 713.849us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 207.900s 713.849us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 102.950s 14277.945us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 102.950s 14277.945us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 102.950s 14277.945us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 102.950s 14277.945us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 102.950s 14277.945us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 207.900s 713.849us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 207.900s 713.849us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 6.770s 225.660us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 6.770s 225.660us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 6.770s 225.660us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 88.180s 7326.458us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 102.950s 14277.945us 1 1 100.00
rom_ctrl_kmac_err_chk 10.990s 817.556us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 102.950s 14277.945us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 102.950s 14277.945us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 102.950s 14277.945us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 36.280s 3758.761us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 207.900s 713.849us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 70.960s 3005.847us 1 1 100.00