Simulation Results: rstmgr

 
08/04/2026 18:06:49 DVSim: v1.17.3 sha: 007b0cf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.81 %
  • code
  • 99.29 %
  • assert
  • 97.86 %
  • func
  • 96.27 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.75 %
  • toggle
  • 99.08 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.230s 261.373us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.760s 115.828us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.760s 86.239us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 2.150s 275.525us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.690s 400.829us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 0.870s 100.899us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.760s 86.239us 1 1 100.00
rstmgr_csr_aliasing 1.690s 400.829us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.760s 175.856us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.520s 395.041us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.030s 163.326us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 3.980s 1580.083us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 3.980s 1580.083us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 3.980s 1580.083us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 3.980s 1580.083us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 24.880s 9201.653us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.700s 87.940us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.060s 214.744us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.060s 214.744us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.760s 115.828us 1 1 100.00
rstmgr_csr_rw 0.760s 86.239us 1 1 100.00
rstmgr_csr_aliasing 1.690s 400.829us 1 1 100.00
rstmgr_same_csr_outstanding 0.990s 114.272us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.760s 115.828us 1 1 100.00
rstmgr_csr_rw 0.760s 86.239us 1 1 100.00
rstmgr_csr_aliasing 1.690s 400.829us 1 1 100.00
rstmgr_same_csr_outstanding 0.990s 114.272us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 9.450s 8574.188us 1 1 100.00
rstmgr_tl_intg_err 1.490s 490.247us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 9.450s 8574.188us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 9.450s 8574.188us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 1.490s 490.247us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 0.820s 107.414us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 4.110s 1277.907us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 0.970s 301.499us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 9.450s 8574.188us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.760s 86.239us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.760s 86.239us 1 1 100.00