Simulation Results: rv_timer

 
08/04/2026 18:06:49 DVSim: v1.17.3 sha: 007b0cf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.37 %
  • code
  • 100.00 %
  • assert
  • 96.82 %
  • func
  • 95.29 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.680s 195.620us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.550s 18.720us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.550s 14.033us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.740s 598.475us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.690s 229.293us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.620s 66.462us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.550s 14.033us 1 1 100.00
rv_timer_csr_aliasing 0.690s 229.293us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.800s 632.528us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 1.480s 3407.445us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 327.760s 1036552.988us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 327.760s 1036552.988us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 3.930s 4024.808us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.530s 30.520us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.530s 44.425us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.200s 63.222us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.200s 63.222us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.550s 18.720us 1 1 100.00
rv_timer_csr_rw 0.550s 14.033us 1 1 100.00
rv_timer_csr_aliasing 0.690s 229.293us 1 1 100.00
rv_timer_same_csr_outstanding 0.700s 36.534us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.550s 18.720us 1 1 100.00
rv_timer_csr_rw 0.550s 14.033us 1 1 100.00
rv_timer_csr_aliasing 0.690s 229.293us 1 1 100.00
rv_timer_same_csr_outstanding 0.700s 36.534us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.760s 78.870us 1 1 100.00
rv_timer_tl_intg_err 1.070s 520.030us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.070s 520.030us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.580s 130.380us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 1.150s 42.642us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 20.040s 10699.671us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == *
rv_timer_min 106221379025717254180903306184772349311909575800221834611305385975994160910438 80
UVM_FATAL @ 130380353 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x55082704) == 0x1
UVM_INFO @ 130380353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 79849050037530117218855416743141292737434951790188023836169191124668621131874 80
UVM_FATAL @ 632528134 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xf849b04) == 0x1
UVM_INFO @ 632528134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:346) [scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (* [*] vs * [*])
rv_timer_max 87383461360687703332966348495114883988184107118771647990747883720337890410503 80
UVM_ERROR @ 42641611 ps: (rv_timer_scoreboard.sv:346) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (0x0 [0] vs 0x1 [1])
UVM_INFO @ 42641611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---