Simulation Results

Simulation Results: spi_device/1r1w

08/04/2026 18:06:49 DVSim: v1.17.3 sha: 007b0cf json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
86.20 %

code
93.09 %

assert
94.64 %

func
70.88 %

line
99.04 %

branch
98.21 %

cond
95.65 %

toggle
83.19 %

FSM
89.36 %

Validation stages

V1		100.00%
V2		92.31%
V2S		100.00%
unmapped		100.00%

8/8 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	spi_device_flash_and_tpm	28.560s	21434.814us	1	1	100.00
csr_hw_reset				1	1	100.00
	spi_device_csr_hw_reset	0.780s	66.722us	1	1	100.00
csr_rw				1	1	100.00
	spi_device_csr_rw	1.730s	148.527us	1	1	100.00
csr_bit_bash				1	1	100.00
	spi_device_csr_bit_bash	16.910s	7571.576us	1	1	100.00
csr_aliasing				1	1	100.00
	spi_device_csr_aliasing	5.300s	1190.174us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	spi_device_csr_mem_rw_with_rand_reset	1.390s	57.511us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	spi_device_csr_rw	1.730s	148.527us	1	1	100.00
	spi_device_csr_aliasing	5.300s	1190.174us	1	1	100.00
mem_walk				1	1	100.00
	spi_device_mem_walk	0.600s	10.390us	1	1	100.00
mem_partial_access				1	1	100.00
	spi_device_mem_partial_access	1.000s	47.230us	1	1	100.00

24/26 passed

92.31 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
csb_read				1	1	100.00
	spi_device_csb_read	0.730s	18.976us	1	1	100.00
mem_parity				0	1	0.00
	spi_device_mem_parity	0.670s	0.950us	0	1	0.00
mem_cfg				0	1	0.00
	spi_device_ram_cfg	0.640s	3.722us	0	1	0.00
tpm_read				1	1	100.00
	spi_device_tpm_rw	0.680s	80.732us	1	1	100.00
tpm_write				1	1	100.00
	spi_device_tpm_rw	0.680s	80.732us	1	1	100.00
tpm_hw_reg				2	2	100.00
	spi_device_tpm_read_hw_reg	4.590s	10574.469us	1	1	100.00
	spi_device_tpm_sts_read	0.780s	153.341us	1	1	100.00
tpm_fully_random_case				1	1	100.00
	spi_device_tpm_all	15.180s	2770.402us	1	1	100.00
pass_cmd_filtering				2	2	100.00
	spi_device_pass_cmd_filtering	4.980s	3050.699us	1	1	100.00
	spi_device_flash_all	66.610s	8750.368us	1	1	100.00
pass_addr_translation				2	2	100.00
	spi_device_pass_addr_payload_swap	1.640s	156.056us	1	1	100.00
	spi_device_flash_all	66.610s	8750.368us	1	1	100.00
pass_payload_translation				2	2	100.00
	spi_device_pass_addr_payload_swap	1.640s	156.056us	1	1	100.00
	spi_device_flash_all	66.610s	8750.368us	1	1	100.00
cmd_info_slots				1	1	100.00
	spi_device_flash_all	66.610s	8750.368us	1	1	100.00
cmd_read_status				2	2	100.00
	spi_device_intercept	5.700s	2848.451us	1	1	100.00
	spi_device_flash_all	66.610s	8750.368us	1	1	100.00
cmd_read_jedec				2	2	100.00
	spi_device_intercept	5.700s	2848.451us	1	1	100.00
	spi_device_flash_all	66.610s	8750.368us	1	1	100.00
cmd_read_sfdp				2	2	100.00
	spi_device_intercept	5.700s	2848.451us	1	1	100.00
	spi_device_flash_all	66.610s	8750.368us	1	1	100.00
cmd_fast_read				2	2	100.00
	spi_device_intercept	5.700s	2848.451us	1	1	100.00
	spi_device_flash_all	66.610s	8750.368us	1	1	100.00
cmd_read_pipeline				2	2	100.00
	spi_device_intercept	5.700s	2848.451us	1	1	100.00
	spi_device_flash_all	66.610s	8750.368us	1	1	100.00
flash_cmd_upload				1	1	100.00
	spi_device_upload	7.900s	11685.459us	1	1	100.00
mailbox_command				1	1	100.00
	spi_device_mailbox	2.220s	385.309us	1	1	100.00
mailbox_cross_outside_command				1	1	100.00
	spi_device_mailbox	2.220s	385.309us	1	1	100.00
mailbox_cross_inside_command				1	1	100.00
	spi_device_mailbox	2.220s	385.309us	1	1	100.00
cmd_read_buffer				2	2	100.00
	spi_device_flash_mode	39.250s	4071.670us	1	1	100.00
	spi_device_read_buffer_direct	2.520s	123.754us	1	1	100.00
cmd_dummy_cycle				2	2	100.00
	spi_device_mailbox	2.220s	385.309us	1	1	100.00
	spi_device_flash_all	66.610s	8750.368us	1	1	100.00
quad_spi				1	1	100.00
	spi_device_flash_all	66.610s	8750.368us	1	1	100.00
dual_spi				1	1	100.00
	spi_device_flash_all	66.610s	8750.368us	1	1	100.00
4b_3b_feature				1	1	100.00
	spi_device_cfg_cmd	1.680s	89.297us	1	1	100.00
write_enable_disable				1	1	100.00
	spi_device_cfg_cmd	1.680s	89.297us	1	1	100.00
TPM_with_flash_or_passthrough_mode				1	1	100.00
	spi_device_flash_and_tpm	28.560s	21434.814us	1	1	100.00
tpm_and_flash_trans_with_min_inactive_time				1	1	100.00
	spi_device_flash_and_tpm_min_idle	38.920s	7923.083us	1	1	100.00
stress_all				1	1	100.00
	spi_device_stress_all	78.640s	21812.904us	1	1	100.00
alert_test				1	1	100.00
	spi_device_alert_test	0.650s	14.639us	1	1	100.00
intr_test				1	1	100.00
	spi_device_intr_test	0.670s	12.486us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	spi_device_tl_errors	3.730s	832.143us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	spi_device_tl_errors	3.730s	832.143us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	spi_device_csr_hw_reset	0.780s	66.722us	1	1	100.00
	spi_device_csr_rw	1.730s	148.527us	1	1	100.00
	spi_device_csr_aliasing	5.300s	1190.174us	1	1	100.00
	spi_device_same_csr_outstanding	1.470s	319.585us	1	1	100.00
tl_d_partial_access				4	4	100.00
	spi_device_csr_hw_reset	0.780s	66.722us	1	1	100.00
	spi_device_csr_rw	1.730s	148.527us	1	1	100.00
	spi_device_csr_aliasing	5.300s	1190.174us	1	1	100.00
	spi_device_same_csr_outstanding	1.470s	319.585us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	spi_device_tl_intg_err	9.540s	2501.921us	1	1	100.00
	spi_device_sec_cm	0.810s	44.947us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	spi_device_tl_intg_err	9.540s	2501.921us	1	1	100.00

unmapped

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				1	1	100.00
	spi_device_flash_mode_ignore_cmds	50.720s	53291.806us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*])
	spi_device_mem_parity	108279854793875059793448779151899289465584687058816811277179700672695304692169	81	UVM_ERROR @ 762028 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[68]) Either the name is incorrect, or you may not have PLI/ACC visibility to that name UVM_ERROR @ 762028 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data)) UVM_ERROR @ 762028 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[964]) Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [] vs [*])
	spi_device_ram_cfg	23001353796213543383664415772361101276433242257634764948218902732005941306300	81	UVM_ERROR @ 932692 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x313d68 [1100010011110101101000] vs 0x0 [0]) UVM_ERROR @ 993692 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x7b296a [11110110010100101101010] vs 0x0 [0]) UVM_ERROR @ 1030692 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x522c13 [10100100010110000010011] vs 0x0 [0]) UVM_ERROR @ 1112692 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xedb1f6 [111011011011000111110110] vs 0x0 [0]) UVM_ERROR @ 1174692 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc030dd [110000000011000011011101] vs 0x0 [0])