Simulation Results: spi_device/2p

 
08/04/2026 18:06:49 DVSim: v1.17.3 sha: 007b0cf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.92 %
  • code
  • 94.10 %
  • assert
  • 94.62 %
  • func
  • 69.05 %
  • line
  • 99.09 %
  • branch
  • 98.28 %
  • cond
  • 96.02 %
  • toggle
  • 87.74 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 11.020s 1459.036us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.020s 23.721us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.460s 71.064us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 22.690s 9811.579us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 14.940s 1211.930us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 1.440s 28.552us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.460s 71.064us 1 1 100.00
spi_device_csr_aliasing 14.940s 1211.930us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.630s 18.368us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.000s 270.905us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.710s 55.173us 1 1 100.00
mem_parity 1 1 100.00
spi_device_mem_parity 0.860s 16.786us 1 1 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 0.630s 27.571us 1 1 100.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.120s 217.290us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.120s 217.290us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 1.020s 3975.908us 1 1 100.00
spi_device_tpm_sts_read 0.790s 355.957us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 11.060s 15810.577us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 11.150s 6983.079us 1 1 100.00
spi_device_flash_all 124.150s 29145.965us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 2.510s 829.866us 1 1 100.00
spi_device_flash_all 124.150s 29145.965us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 2.510s 829.866us 1 1 100.00
spi_device_flash_all 124.150s 29145.965us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 124.150s 29145.965us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 1.640s 77.987us 1 1 100.00
spi_device_flash_all 124.150s 29145.965us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 1.640s 77.987us 1 1 100.00
spi_device_flash_all 124.150s 29145.965us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 1.640s 77.987us 1 1 100.00
spi_device_flash_all 124.150s 29145.965us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 1.640s 77.987us 1 1 100.00
spi_device_flash_all 124.150s 29145.965us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 1.640s 77.987us 1 1 100.00
spi_device_flash_all 124.150s 29145.965us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 5.050s 2124.481us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 6.210s 282.691us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 6.210s 282.691us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 6.210s 282.691us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 5.410s 318.327us 1 1 100.00
spi_device_read_buffer_direct 4.110s 1517.045us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 6.210s 282.691us 1 1 100.00
spi_device_flash_all 124.150s 29145.965us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 124.150s 29145.965us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 124.150s 29145.965us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 4.700s 3429.645us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 4.700s 3429.645us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 11.020s 1459.036us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 62.260s 10883.892us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 106.060s 229216.530us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.650s 29.145us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.650s 15.100us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 2.280s 117.062us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 2.280s 117.062us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.020s 23.721us 1 1 100.00
spi_device_csr_rw 1.460s 71.064us 1 1 100.00
spi_device_csr_aliasing 14.940s 1211.930us 1 1 100.00
spi_device_same_csr_outstanding 1.460s 81.660us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.020s 23.721us 1 1 100.00
spi_device_csr_rw 1.460s 71.064us 1 1 100.00
spi_device_csr_aliasing 14.940s 1211.930us 1 1 100.00
spi_device_same_csr_outstanding 1.460s 81.660us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_tl_intg_err 8.080s 901.724us 1 1 100.00
spi_device_sec_cm 0.950s 174.387us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 8.080s 901.724us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 26.180s 13579.357us 1 1 100.00