Simulation Results: spi_host

 
08/04/2026 18:06:49 DVSim: v1.17.3 sha: 007b0cf json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.33 %
  • code
  • 95.03 %
  • assert
  • 94.13 %
  • func
  • 87.82 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 18.000s 3308.646us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 83.466us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 55.199us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 66.051us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 18.667us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 1.000s 97.287us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 55.199us 1 1 100.00
spi_host_csr_aliasing 1.000s 18.667us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 37.494us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 44.196us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 2.000s 20.138us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 4.000s 152.770us 1 1 100.00
spi_host_error_cmd 2.000s 18.959us 1 1 100.00
spi_host_event 9.000s 1410.261us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 4.000s 101.134us 1 1 100.00
speed 1 1 100.00
spi_host_speed 4.000s 101.134us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 4.000s 101.134us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 5.000s 264.711us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 401.408us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 4.000s 101.134us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 4.000s 101.134us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 18.000s 3308.646us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 18.000s 3308.646us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 2.000s 143.232us 1 1 100.00
spien 1 1 100.00
spi_host_spien 5.000s 791.860us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 79.000s 11268.640us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 2.000s 88.999us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 4.000s 152.770us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 39.781us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 2.000s 21.863us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 3.000s 536.410us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 3.000s 536.410us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 83.466us 1 1 100.00
spi_host_csr_rw 1.000s 55.199us 1 1 100.00
spi_host_csr_aliasing 1.000s 18.667us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 19.494us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 83.466us 1 1 100.00
spi_host_csr_rw 1.000s 55.199us 1 1 100.00
spi_host_csr_aliasing 1.000s 18.667us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 19.494us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_sec_cm 1.000s 371.938us 1 1 100.00
spi_host_tl_intg_err 2.000s 52.598us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 52.598us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_host_upper_range_clkdiv 170.000s 17112.753us 1 1 100.00