Simulation Results: sram_ctrl/main

 
08/04/2026 18:06:49 DVSim: v1.17.3 sha: 007b0cf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.96 %
  • code
  • 95.49 %
  • assert
  • 95.92 %
  • func
  • 96.47 %
  • line
  • 99.16 %
  • branch
  • 97.67 %
  • cond
  • 91.26 %
  • toggle
  • 89.35 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
90.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 11.030s 16910.466us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.670s 151.130us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.650s 21.729us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.490s 124.715us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.660s 53.278us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.410s 1562.521us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.650s 21.729us 1 1 100.00
sram_ctrl_csr_aliasing 0.660s 53.278us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 237.380s 38261.912us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 55.720s 2798.688us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 650.240s 83015.021us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 238.120s 4766.304us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 535.240s 11077.300us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 212.750s 3975.043us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 15.900s 7207.627us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 451.200s 20400.435us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.500s 389.240us 1 1 100.00
sram_ctrl_partial_access_b2b 248.550s 111091.491us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 43.740s 2994.396us 1 1 100.00
sram_ctrl_throughput_w_partial_write 7.360s 2775.517us 1 1 100.00
sram_ctrl_throughput_w_readback 46.810s 912.507us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 48.550s 5773.687us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.060s 2232.479us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 5893.650s 389608.725us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.600s 41.892us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.240s 147.830us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.240s 147.830us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.670s 151.130us 1 1 100.00
sram_ctrl_csr_rw 0.650s 21.729us 1 1 100.00
sram_ctrl_csr_aliasing 0.660s 53.278us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.700s 50.834us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.670s 151.130us 1 1 100.00
sram_ctrl_csr_rw 0.650s 21.729us 1 1 100.00
sram_ctrl_csr_aliasing 0.660s 53.278us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.700s 50.834us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 29.440s 28217.139us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_tl_intg_err 1.600s 433.145us 1 1 100.00
sram_ctrl_sec_cm 0.610s 2.780us 0 1 0.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.610s 2.780us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.600s 433.145us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 48.550s 5773.687us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 48.550s 5773.687us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.650s 21.729us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 451.200s 20400.435us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 451.200s 20400.435us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 451.200s 20400.435us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 15.900s 7207.627us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 3.570s 668.643us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 29.440s 28217.139us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 3.950s 3686.642us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 11.030s 16910.466us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 11.030s 16910.466us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 451.200s 20400.435us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.610s 2.780us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 15.900s 7207.627us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.610s 2.780us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.610s 2.780us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 11.030s 16910.466us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.610s 2.780us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 8.000s 384.183us 1 1 100.00

Error Messages

   Test seed line log context
Offending '(depth_o <= *'(Depth))'
sram_ctrl_sec_cm 78731373295367133048004475482422049368726128427700099409191961784647806144610 104
Offending '(depth_o <= 2'(Depth))'
UVM_ERROR @ 2779814 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
UVM_INFO @ 2779814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---