Simulation Results: sram_ctrl/ret

 
08/04/2026 18:06:49 DVSim: v1.17.3 sha: 007b0cf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.10 %
  • code
  • 87.76 %
  • assert
  • 95.61 %
  • func
  • 95.92 %
  • line
  • 97.31 %
  • branch
  • 95.01 %
  • cond
  • 90.46 %
  • toggle
  • 89.35 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
90.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 8.140s 750.921us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.630s 33.865us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.630s 18.481us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.050s 244.827us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.640s 15.361us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 0.810s 33.181us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.630s 18.481us 1 1 100.00
sram_ctrl_csr_aliasing 0.640s 15.361us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 3.250s 138.107us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 1.980s 163.082us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 510.410s 57325.248us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 162.750s 2585.043us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 41.750s 4573.549us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 97.330s 5303.135us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 4.680s 2080.399us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 163.650s 8170.432us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 12.450s 305.670us 1 1 100.00
sram_ctrl_partial_access_b2b 350.820s 89757.855us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 12.990s 506.817us 1 1 100.00
sram_ctrl_throughput_w_partial_write 17.830s 113.833us 1 1 100.00
sram_ctrl_throughput_w_readback 2.890s 160.753us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 499.610s 49307.856us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 0.670s 48.253us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 202.940s 25130.742us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.610s 16.908us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 1.760s 105.891us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 1.760s 105.891us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.630s 33.865us 1 1 100.00
sram_ctrl_csr_rw 0.630s 18.481us 1 1 100.00
sram_ctrl_csr_aliasing 0.640s 15.361us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.710s 46.395us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.630s 33.865us 1 1 100.00
sram_ctrl_csr_rw 0.630s 18.481us 1 1 100.00
sram_ctrl_csr_aliasing 0.640s 15.361us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.710s 46.395us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.090s 419.437us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_tl_intg_err 1.260s 113.354us 1 1 100.00
sram_ctrl_sec_cm 0.670s 4.057us 0 1 0.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.670s 4.057us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.260s 113.354us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 499.610s 49307.856us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 499.610s 49307.856us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.630s 18.481us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 163.650s 8170.432us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 163.650s 8170.432us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 163.650s 8170.432us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 4.680s 2080.399us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 0.900s 139.170us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.090s 419.437us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 0.880s 93.532us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 8.140s 750.921us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 8.140s 750.921us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 163.650s 8170.432us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.670s 4.057us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 4.680s 2080.399us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.670s 4.057us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.670s 4.057us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 8.140s 750.921us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.670s 4.057us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 31.950s 2707.024us 1 1 100.00

Error Messages

   Test seed line log context
Offending '(depth_o <= *'(Depth))'
sram_ctrl_sec_cm 115582439568722974837772692855608516168965099520933690616114448155181277440501 106
Offending '(depth_o <= 2'(Depth))'
UVM_ERROR @ 4056721 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
UVM_INFO @ 4056721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---