Simulation Results: sysrst_ctrl

 
08/04/2026 18:06:49 DVSim: v1.17.3 sha: 007b0cf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.52 %
  • code
  • 90.47 %
  • assert
  • 89.46 %
  • func
  • 58.64 %
  • line
  • 95.55 %
  • branch
  • 96.29 %
  • cond
  • 93.21 %
  • toggle
  • 100.00 %
  • FSM
  • 67.31 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 1.010s 2126.206us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 1.530s 2478.947us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 1.980s 2424.023us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 2.710s 2529.749us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 3.200s 6091.332us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 3.910s 2040.276us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 182.290s 73626.908us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 2.640s 3389.509us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 3.720s 2051.563us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 3.910s 2040.276us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.640s 3389.509us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 14.500s 34094.342us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 122.080s 92873.220us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 3.870s 3745.945us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 6.480s 5826.462us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 1.670s 2527.741us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 4.250s 2110.889us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 5.440s 5572.346us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 2.780s 2611.508us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 1.230s 4699.636us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 14.310s 33411.001us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 4.700s 12101.975us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 2.180s 2017.735us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 2.260s 2022.976us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 3.880s 2272.767us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 3.880s 2272.767us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 3.200s 6091.332us 1 1 100.00
sysrst_ctrl_csr_rw 3.910s 2040.276us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.640s 3389.509us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 25.100s 7662.512us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 3.200s 6091.332us 1 1 100.00
sysrst_ctrl_csr_rw 3.910s 2040.276us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.640s 3389.509us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 25.100s 7662.512us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 69.680s 42009.264us 1 1 100.00
sysrst_ctrl_tl_intg_err 39.770s 22232.893us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 39.770s 22232.893us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 2.370s 3941.743us 1 1 100.00