Simulation Results: uart

 
08/04/2026 18:06:49 DVSim: v1.17.3 sha: 007b0cf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.08 %
  • code
  • 95.61 %
  • assert
  • 97.12 %
  • func
  • 50.51 %
  • line
  • 99.17 %
  • branch
  • 97.44 %
  • cond
  • 94.52 %
  • toggle
  • 91.32 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.330s 649.132us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.530s 12.322us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.550s 14.567us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.050s 39.292us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.680s 117.658us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.680s 61.640us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.550s 14.567us 1 1 100.00
uart_csr_aliasing 0.680s 117.658us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 61.080s 71365.097us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.330s 649.132us 1 1 100.00
uart_tx_rx 61.080s 71365.097us 1 1 100.00
parity_error 2 2 100.00
uart_intr 53.970s 41949.536us 1 1 100.00
uart_rx_parity_err 23.870s 53095.987us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 61.080s 71365.097us 1 1 100.00
uart_intr 53.970s 41949.536us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 23.710s 90182.613us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 69.710s 144589.913us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 15.910s 27058.349us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 53.970s 41949.536us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 53.970s 41949.536us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 53.970s 41949.536us 1 1 100.00
perf 1 1 100.00
uart_perf 387.070s 12064.588us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 1.580s 4583.491us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 1.580s 4583.491us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 6.450s 22742.086us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 1.030s 1837.797us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.380s 732.308us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 20.630s 6587.627us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 624.920s 146678.190us 1 1 100.00
stress_all 0 1 0.00
uart_stress_all 101.270s 64788.520us 0 1 0.00
alert_test 1 1 100.00
uart_alert_test 0.550s 34.311us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.560s 51.636us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.400s 38.324us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.400s 38.324us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.530s 12.322us 1 1 100.00
uart_csr_rw 0.550s 14.567us 1 1 100.00
uart_csr_aliasing 0.680s 117.658us 1 1 100.00
uart_same_csr_outstanding 0.580s 163.860us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.530s 12.322us 1 1 100.00
uart_csr_rw 0.550s 14.567us 1 1 100.00
uart_csr_aliasing 0.680s 117.658us 1 1 100.00
uart_same_csr_outstanding 0.580s 163.860us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.730s 41.814us 1 1 100.00
uart_tl_intg_err 0.770s 376.525us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 0.770s 376.525us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
uart_stress_all_with_rand_reset 11.690s 8201.181us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = *
uart_noise_filter 83151239796194474134756779901845739378086692340377043240697406347068102747042 80
UVM_ERROR @ 20927280050 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 20927280050 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 20927280050 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 21320241527 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 12, clk_pulses: 0
UVM_ERROR @ 21320324861 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (20 [0x14] vs 255 [0xff]) reg name: uart_reg_block.rdata
uart_stress_all 39239558899918609531101244756782075111227104612882537453639866241045682202602 83
UVM_ERROR @ 64448719828 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 64448719828 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 64448719828 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 64536029828 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 64665329828 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = *
uart_stress_all_with_rand_reset 12049202109235102714802658189673615368335098455351186067902662280080037477414 116
UVM_ERROR @ 6439875416 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 6450000497 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 6558834701 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 6, clk_pulses: 0
UVM_ERROR @ 6559209704 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 6559418039 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (100 [0x64] vs 125 [0x7d]) reg name: uart_reg_block.rdata