Simulation Results: adc_ctrl

 
13/04/2026 19:14:24 DVSim: v1.30.1 sha: 4ae05e3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 69.95 %
  • code
  • 95.81 %
  • assert
  • 95.79 %
  • func
  • 18.24 %
  • line
  • 99.05 %
  • branch
  • 97.71 %
  • cond
  • 93.09 %
  • toggle
  • 100.00 %
  • FSM
  • 89.19 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 4.030s 5838.197us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 3.160s 1195.530us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 1.350s 588.492us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 16.490s 20207.275us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 2.750s 1014.627us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.320s 629.685us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 1.350s 588.492us 1 1 100.00
adc_ctrl_csr_aliasing 2.750s 1014.627us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 1 1 100.00
adc_ctrl_filters_polled 64.830s 167445.896us 1 1 100.00
filters_polled_fixed 1 1 100.00
adc_ctrl_filters_polled_fixed 754.410s 492948.610us 1 1 100.00
filters_interrupt 1 1 100.00
adc_ctrl_filters_interrupt 747.200s 490277.414us 1 1 100.00
filters_interrupt_fixed 1 1 100.00
adc_ctrl_filters_interrupt_fixed 111.710s 495523.678us 1 1 100.00
filters_wakeup 1 1 100.00
adc_ctrl_filters_wakeup 84.940s 204201.930us 1 1 100.00
filters_wakeup_fixed 1 1 100.00
adc_ctrl_filters_wakeup_fixed 64.150s 397980.397us 1 1 100.00
filters_both 1 1 100.00
adc_ctrl_filters_both 226.620s 539111.359us 1 1 100.00
clock_gating 1 1 100.00
adc_ctrl_clock_gating 346.090s 207082.707us 1 1 100.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 2.390s 3615.187us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 22.340s 31799.469us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 198.810s 109679.184us 1 1 100.00
stress_all 1 1 100.00
adc_ctrl_stress_all 127.740s 558588.324us 1 1 100.00
alert_test 1 1 100.00
adc_ctrl_alert_test 1.140s 372.448us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 1.880s 346.406us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 2.340s 439.484us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 2.340s 439.484us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 3.160s 1195.530us 1 1 100.00
adc_ctrl_csr_rw 1.350s 588.492us 1 1 100.00
adc_ctrl_csr_aliasing 2.750s 1014.627us 1 1 100.00
adc_ctrl_same_csr_outstanding 3.630s 2288.167us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 3.160s 1195.530us 1 1 100.00
adc_ctrl_csr_rw 1.350s 588.492us 1 1 100.00
adc_ctrl_csr_aliasing 2.750s 1014.627us 1 1 100.00
adc_ctrl_same_csr_outstanding 3.630s 2288.167us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 9.070s 3908.672us 1 1 100.00
adc_ctrl_tl_intg_err 6.140s 9130.498us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 6.140s 9130.498us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
adc_ctrl_stress_all_with_rand_reset 13.230s 43085.588us 1 1 100.00