Simulation Results: chip

 
13/04/2026 19:14:24 DVSim: v1.30.1 sha: 4ae05e3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 78.37 %
  • code
  • 85.07 %
  • assert
  • 97.25 %
  • func
  • 52.79 %
  • line
  • 94.40 %
  • branch
  • 93.66 %
  • cond
  • 88.91 %
  • toggle
  • 91.22 %
  • FSM
  • 57.14 %
Validation stages
V1
94.44%
V2
91.37%
V2S
100.00%
V3
65.38%
unmapped
70.00%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 4 4 100.00
chip_sw_example_flash 129.930s 2698.941us 1 1 100.00
chip_sw_example_rom 65.930s 2815.304us 1 1 100.00
chip_sw_example_manufacturer 165.750s 2878.396us 1 1 100.00
chip_sw_example_concurrency 180.270s 3412.125us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 304.670s 7667.716us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 253.970s 4076.066us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 3423.650s 43150.778us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 5301.730s 38789.975us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
chip_csr_mem_rw_with_rand_reset 64.880s 2359.415us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 5301.730s 38789.975us 1 1 100.00
chip_csr_rw 253.970s 4076.066us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 6.580s 210.426us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 303.630s 4302.473us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 303.630s 4302.473us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 303.630s 4302.473us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 380.720s 4903.852us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 380.720s 4903.852us 1 1 100.00
chip_sw_uart_tx_rx_idx1 318.260s 4658.093us 1 1 100.00
chip_sw_uart_tx_rx_idx2 341.250s 4526.515us 1 1 100.00
chip_sw_uart_tx_rx_idx3 340.910s 3746.516us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 1664.060s 13717.352us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 1039.640s 8624.939us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 314.270s 5343.011us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 207.070s 5512.240us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 207.070s 5512.240us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 211.700s 3321.094us 1 1 100.00
chip_sw_sleep_pin_wake 1 1 100.00
chip_sw_sleep_pin_wake 324.620s 6888.165us 1 1 100.00
chip_sw_sleep_pin_retention 1 1 100.00
chip_sw_sleep_pin_retention 174.360s 3891.990us 1 1 100.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 131.340s 3610.257us 1 1 100.00
chip_tap_straps_testunlock0 263.590s 5204.975us 1 1 100.00
chip_tap_straps_rma 146.440s 3177.680us 1 1 100.00
chip_tap_straps_prod 89.170s 2638.325us 1 1 100.00
chip_sw_pattgen_ios 1 1 100.00
chip_sw_pattgen_ios 159.890s 2824.080us 1 1 100.00
chip_sw_sleep_pwm_pulses 1 1 100.00
chip_sw_sleep_pwm_pulses 796.540s 8621.203us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 388.230s 6237.617us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 388.230s 6237.617us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 678.890s 8834.018us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 1207.750s 12547.094us 0 1 0.00
chip_sw_ast_sys_clk_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 356.870s 4381.728us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 630.490s 6214.308us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3634.860s 18829.818us 1 1 100.00
chip_sw_aes_enc_jitter_en 190.700s 3096.167us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 584.320s 6764.676us 1 1 100.00
chip_sw_hmac_enc_jitter_en 178.090s 2750.586us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 806.000s 7528.503us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 197.980s 3063.934us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 368.750s 5335.597us 1 1 100.00
chip_sw_clkmgr_jitter 166.580s 2732.126us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 170.960s 3730.803us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 1 2 50.00
chip_sw_sensor_ctrl_alert 157.610s 2933.544us 0 1 0.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 239.570s 5582.965us 1 1 100.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 123.940s 2885.974us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 239.570s 5582.965us 1 1 100.00
chip_sw_smoketest 17 17 100.00
chip_sw_flash_scrambling_smoketest 164.860s 2460.149us 1 1 100.00
chip_sw_aes_smoketest 167.070s 3452.134us 1 1 100.00
chip_sw_aon_timer_smoketest 196.170s 3731.514us 1 1 100.00
chip_sw_clkmgr_smoketest 160.720s 3054.118us 1 1 100.00
chip_sw_csrng_smoketest 180.820s 3028.017us 1 1 100.00
chip_sw_entropy_src_smoketest 858.870s 6627.975us 1 1 100.00
chip_sw_gpio_smoketest 168.100s 3067.221us 1 1 100.00
chip_sw_hmac_smoketest 282.760s 3500.849us 1 1 100.00
chip_sw_kmac_smoketest 216.340s 3824.594us 1 1 100.00
chip_sw_otbn_smoketest 685.370s 6047.546us 1 1 100.00
chip_sw_pwrmgr_smoketest 203.560s 5043.580us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 329.290s 5588.873us 1 1 100.00
chip_sw_rv_plic_smoketest 127.080s 3118.862us 1 1 100.00
chip_sw_rv_timer_smoketest 161.040s 2849.796us 1 1 100.00
chip_sw_rstmgr_smoketest 153.630s 3467.240us 1 1 100.00
chip_sw_sram_ctrl_smoketest 137.210s 2530.146us 1 1 100.00
chip_sw_uart_smoketest 187.710s 3385.505us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 181.070s 3117.082us 1 1 100.00
chip_sw_rom_functests 0 1 0.00
rom_keymgr_functest 306.090s 4928.120us 0 1 0.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 9114.870s 63113.447us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 2990.440s 15223.450us 1 1 100.00
chip_sw_rom_raw_unlock 1 1 100.00
rom_raw_unlock 126.260s 4894.905us 1 1 100.00
chip_sw_power_idle_load 0 1 0.00
chip_sw_power_idle_load 208.240s 3923.713us 0 1 0.00
chip_sw_power_sleep_load 0 1 0.00
chip_sw_power_sleep_load 176.220s 2989.390us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 7409.740s 55394.862us 1 1 100.00
chip_sw_inject_scramble_seed 1 1 100.00
chip_sw_inject_scramble_seed 9003.880s 57216.142us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 65.450s 2086.496us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 65.450s 2086.496us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
chip_csr_aliasing 5301.730s 38789.975us 1 1 100.00
chip_same_csr_outstanding 1796.430s 16270.338us 1 1 100.00
chip_csr_hw_reset 304.670s 7667.716us 1 1 100.00
chip_csr_rw 253.970s 4076.066us 1 1 100.00
tl_d_partial_access 4 4 100.00
chip_csr_aliasing 5301.730s 38789.975us 1 1 100.00
chip_same_csr_outstanding 1796.430s 16270.338us 1 1 100.00
chip_csr_hw_reset 304.670s 7667.716us 1 1 100.00
chip_csr_rw 253.970s 4076.066us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 20.490s 331.900us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 6.370s 47.470us 1 1 100.00
xbar_smoke_large_delays 49.080s 7853.018us 1 1 100.00
xbar_smoke_slow_rsp 42.390s 4647.375us 1 1 100.00
xbar_random_zero_delays 32.500s 593.775us 1 1 100.00
xbar_random_large_delays 331.180s 55234.396us 1 1 100.00
xbar_random_slow_rsp 253.450s 27818.061us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 7.520s 77.489us 1 1 100.00
xbar_error_and_unmapped_addr 15.720s 205.960us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 10.290s 103.270us 1 1 100.00
xbar_error_and_unmapped_addr 15.720s 205.960us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 20.940s 323.722us 1 1 100.00
xbar_access_same_device_slow_rsp 534.840s 60795.172us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 6.770s 174.856us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 278.330s 4923.010us 1 1 100.00
xbar_stress_all_with_error 118.550s 5019.727us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 42.230s 441.883us 1 1 100.00
xbar_stress_all_with_reset_error 336.230s 6468.396us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 2990.440s 15223.450us 1 1 100.00
rom_e2e_shutdown_output 1 1 100.00
rom_e2e_shutdown_output 2682.600s 26571.001us 1 1 100.00
rom_e2e_shutdown_exception_c 1 1 100.00
rom_e2e_shutdown_exception_c 2876.680s 15515.999us 1 1 100.00
rom_e2e_boot_policy_valid 15 15 100.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 2252.280s 11092.077us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 3018.140s 16014.886us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 3154.540s 15799.284us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 2946.620s 15817.844us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 3034.410s 16340.081us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 2356.470s 12712.576us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 2896.380s 15508.253us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 3149.210s 16148.080us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 3205.560s 17188.227us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 2948.060s 15409.319us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 4017.880s 18661.089us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 5120.830s 24486.290us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 5295.150s 24940.283us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 5211.860s 24287.654us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 5401.480s 23750.430us 1 1 100.00
rom_e2e_sigverify_always 14 15 93.33
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 3905.350s 18316.609us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 5250.340s 24086.630us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 4845.520s 23902.897us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 5282.150s 23626.764us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 4883.010s 23088.816us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 2245.550s 12420.037us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 2897.390s 21014.567us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 2746.820s 14528.936us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 2878.120s 14662.901us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 2563.750s 13617.157us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 2319.490s 13072.684us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 2910.930s 15942.215us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 2986.170s 15840.343us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 2778.280s 15242.233us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 2680.760s 14689.141us 1 1 100.00
rom_e2e_asm_init 5 5 100.00
rom_e2e_asm_init_test_unlocked0 2327.380s 11494.601us 1 1 100.00
rom_e2e_asm_init_dev 3149.500s 17707.838us 1 1 100.00
rom_e2e_asm_init_prod 3038.060s 18736.428us 1 1 100.00
rom_e2e_asm_init_prod_end 2898.630s 15278.234us 1 1 100.00
rom_e2e_asm_init_rma 2953.100s 15794.869us 1 1 100.00
rom_e2e_keymgr_init 2 3 66.67
rom_e2e_keymgr_init_rom_ext_meas 6074.630s 28764.620us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_no_meas 2954.940s 16439.215us 0 1 0.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 5913.320s 29978.241us 1 1 100.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 3167.250s 16567.623us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2905.430s 34954.534us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2905.430s 34954.534us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 136.250s 2871.215us 1 1 100.00
chip_sw_aes_enc_jitter_en 190.700s 3096.167us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 165.070s 3475.054us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 145.160s 2470.331us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_sideload_aes 1633.400s 12323.648us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 169.570s 3580.451us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 434.410s 5341.435us 1 1 100.00
chip_sw_all_escalation_resets 1 1 100.00
chip_sw_all_escalation_resets 339.990s 5902.714us 1 1 100.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 603.270s 5467.007us 1 1 100.00
chip_plic_all_irqs_10 290.600s 3581.062us 1 1 100.00
chip_plic_all_irqs_20 368.530s 4581.255us 1 1 100.00
chip_sw_alert_handler_entropy 1 1 100.00
chip_sw_alert_handler_entropy 190.300s 3369.046us 1 1 100.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 1174.680s 13452.931us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 287.900s 4501.989us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 182.880s 3395.741us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0.000s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 1212.070s 8560.016us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1011.400s 7812.648us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 807.450s 8351.813us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 9971.830s 255540.280us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 212.020s 4259.787us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 203.560s 5043.580us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 212.020s 4259.787us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 569.840s 9373.434us 1 1 100.00
chip_sw_aon_timer_sleep_wdog_bite_reset 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 569.840s 9373.434us 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 251.590s 7329.423us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 380.230s 5412.656us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 577.540s 5984.035us 1 1 100.00
chip_sw_aes_idle 145.160s 2470.331us 1 1 100.00
chip_sw_hmac_enc_idle 208.080s 3415.117us 1 1 100.00
chip_sw_kmac_idle 120.340s 3335.521us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 256.650s 4068.253us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 342.150s 4588.769us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 231.160s 4889.673us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 265.250s 5072.332us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 933.600s 11168.586us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 395.200s 4181.787us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 386.860s 5081.438us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 410.510s 4985.305us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 384.090s 5022.488us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 360.490s 4256.810us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 380.440s 4656.300us 1 1 100.00
chip_sw_ast_clk_outputs 678.890s 8834.018us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 313.270s 6228.837us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 410.510s 4985.305us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 384.090s 5022.488us 1 1 100.00
chip_sw_clkmgr_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 356.870s 4381.728us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 630.490s 6214.308us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3634.860s 18829.818us 1 1 100.00
chip_sw_aes_enc_jitter_en 190.700s 3096.167us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 584.320s 6764.676us 1 1 100.00
chip_sw_hmac_enc_jitter_en 178.090s 2750.586us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 806.000s 7528.503us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 197.980s 3063.934us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 368.750s 5335.597us 1 1 100.00
chip_sw_clkmgr_jitter 166.580s 2732.126us 1 1 100.00
chip_sw_clkmgr_extended_range 11 11 100.00
chip_sw_clkmgr_jitter_reduced_freq 121.900s 3116.231us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 348.430s 4797.064us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 626.730s 7398.031us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 3925.590s 25253.515us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 161.360s 2864.379us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 165.270s 2980.294us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 872.000s 8501.513us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 173.190s 2974.765us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 398.680s 4453.065us 1 1 100.00
chip_sw_flash_init_reduced_freq 1183.040s 22902.684us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 1238.500s 11912.803us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 678.890s 8834.018us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 1 1 100.00
chip_sw_clkmgr_sleep_frequency 341.460s 4526.240us 1 1 100.00
chip_sw_clkmgr_reset_frequency 1 1 100.00
chip_sw_clkmgr_reset_frequency 246.610s 3514.510us 1 1 100.00
chip_sw_clkmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 339.990s 5902.714us 1 1 100.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 1212.070s 8560.016us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 827.980s 7181.055us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 0 1 0.00
chip_sw_csrng_fuse_en_sw_app_read_test 173.020s 3015.097us 0 1 0.00
chip_sw_csrng_lc_hw_debug_en 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 387.630s 5771.975us 1 1 100.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 209.420s 3215.186us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 2603.030s 15769.102us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 126.850s 2767.035us 1 1 100.00
chip_sw_edn_entropy_reqs 718.540s 7036.894us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 126.850s 2767.035us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 827.980s 7181.055us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 179.410s 2889.603us 1 1 100.00
chip_sw_flash_init 1 1 100.00
chip_sw_flash_init 991.660s 21958.761us 1 1 100.00
chip_sw_flash_host_access 2 2 100.00
chip_sw_flash_ctrl_access 616.070s 5829.270us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 630.490s 6214.308us 1 1 100.00
chip_sw_flash_ctrl_ops 2 2 100.00
chip_sw_flash_ctrl_ops 335.020s 4610.213us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 356.870s 4381.728us 1 1 100.00
chip_sw_flash_rma_unlocked 1 1 100.00
chip_sw_flash_rma_unlocked 3752.710s 43242.917us 1 1 100.00
chip_sw_flash_scramble 1 1 100.00
chip_sw_flash_init 991.660s 21958.761us 1 1 100.00
chip_sw_flash_idle_low_power 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 271.870s 4361.863us 1 1 100.00
chip_sw_flash_keymgr_seeds 1 1 100.00
chip_sw_keymgr_key_derivation 1514.840s 12716.789us 1 1 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 149.560s 3410.091us 0 1 0.00
chip_sw_flash_creator_seed_wipe_on_rma 1 1 100.00
chip_sw_flash_rma_unlocked 3752.710s 43242.917us 1 1 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 149.560s 3410.091us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 149.560s 3410.091us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_wr_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 149.560s 3410.091us 0 1 0.00
chip_sw_flash_lc_seed_hw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 149.560s 3410.091us 0 1 0.00
chip_sw_flash_lc_escalate_en 1 1 100.00
chip_sw_all_escalation_resets 339.990s 5902.714us 1 1 100.00
chip_sw_flash_prim_tl_access 1 1 100.00
chip_prim_tl_access 228.140s 9196.565us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 583.610s 5768.314us 1 1 100.00
chip_sw_flash_ctrl_escalation_reset 1 1 100.00
chip_sw_flash_crash_alert 425.270s 5508.805us 1 1 100.00
chip_sw_flash_ctrl_write_clear 1 1 100.00
chip_sw_flash_crash_alert 425.270s 5508.805us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 160.980s 3181.043us 1 1 100.00
chip_sw_hmac_enc_jitter_en 178.090s 2750.586us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 208.080s 3415.117us 1 1 100.00
chip_sw_hmac_all_configurations 1 1 100.00
chip_sw_hmac_oneshot 983.800s 8138.905us 1 1 100.00
chip_sw_hmac_multistream_mode 1 1 100.00
chip_sw_hmac_multistream 672.600s 6196.835us 1 1 100.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 426.220s 5340.898us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 375.630s 5075.679us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 414.820s 5504.082us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 213.220s 3573.615us 1 1 100.00
chip_sw_keymgr_key_derivation 2 2 100.00
chip_sw_keymgr_key_derivation 1514.840s 12716.789us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 806.000s 7528.503us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1 1 100.00
chip_sw_keymgr_sideload_kmac 1132.900s 9491.504us 1 1 100.00
chip_sw_keymgr_sideload_aes 1 1 100.00
chip_sw_keymgr_sideload_aes 1633.400s 12323.648us 1 1 100.00
chip_sw_keymgr_sideload_otbn 1 1 100.00
chip_sw_keymgr_sideload_otbn 2970.950s 16475.686us 1 1 100.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 205.050s 3517.339us 1 1 100.00
chip_sw_kmac_mode_kmac 185.560s 3246.299us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 197.980s 3063.934us 1 1 100.00
chip_sw_kmac_app_keymgr 1 1 100.00
chip_sw_keymgr_key_derivation 1514.840s 12716.789us 1 1 100.00
chip_sw_kmac_app_lc 1 1 100.00
chip_sw_lc_ctrl_transition 275.080s 5932.358us 1 1 100.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 175.280s 2915.852us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 1249.230s 9595.631us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 120.340s 3335.521us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 434.410s 5341.435us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 131.340s 3610.257us 1 1 100.00
chip_tap_straps_rma 146.440s 3177.680us 1 1 100.00
chip_tap_straps_prod 89.170s 2638.325us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 184.810s 3124.621us 1 1 100.00
chip_sw_lc_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 275.080s 5932.358us 1 1 100.00
chip_sw_lc_ctrl_transitions 1 1 100.00
chip_sw_lc_ctrl_transition 275.080s 5932.358us 1 1 100.00
chip_sw_lc_ctrl_kmac_req 1 1 100.00
chip_sw_lc_ctrl_transition 275.080s 5932.358us 1 1 100.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_key_derivation_prod 1791.470s 12754.756us 1 1 100.00
chip_sw_lc_ctrl_broadcast 19 22 86.36
chip_sw_flash_ctrl_lc_rw_en 149.560s 3410.091us 0 1 0.00
chip_sw_flash_rma_unlocked 3752.710s 43242.917us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 186.100s 3018.865us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 561.200s 6874.070us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 545.770s 7023.289us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 485.760s 6022.197us 0 1 0.00
chip_sw_lc_ctrl_transition 275.080s 5932.358us 1 1 100.00
chip_sw_keymgr_key_derivation 1514.840s 12716.789us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 406.750s 9149.933us 1 1 100.00
chip_sw_sram_ctrl_execution_main 623.890s 9461.033us 1 1 100.00
chip_prim_tl_access 228.140s 9196.565us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 313.270s 6228.837us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 395.200s 4181.787us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 386.860s 5081.438us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 410.510s 4985.305us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 384.090s 5022.488us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 360.490s 4256.810us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 380.440s 4656.300us 1 1 100.00
chip_tap_straps_dev 131.340s 3610.257us 1 1 100.00
chip_tap_straps_rma 146.440s 3177.680us 1 1 100.00
chip_tap_straps_prod 89.170s 2638.325us 1 1 100.00
chip_rv_dm_lc_disabled 135.510s 4444.583us 0 1 0.00
chip_lc_scrap 4 4 100.00
chip_sw_lc_ctrl_rma_to_scrap 168.140s 3878.204us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 85.160s 3881.752us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 84.420s 3070.423us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 140.040s 2995.491us 1 1 100.00
chip_lc_test_locked 1 2 50.00
chip_sw_lc_walkthrough_testunlocks 1525.180s 34486.392us 1 1 100.00
chip_rv_dm_lc_disabled 135.510s 4444.583us 0 1 0.00
chip_sw_lc_walkthrough 2 5 40.00
chip_sw_lc_walkthrough_dev 737.210s 11199.885us 0 1 0.00
chip_sw_lc_walkthrough_prod 626.840s 9281.882us 0 1 0.00
chip_sw_lc_walkthrough_prodend 551.550s 10687.688us 1 1 100.00
chip_sw_lc_walkthrough_rma 376.470s 5600.630us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 1525.180s 34486.392us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 3 3 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 74.430s 2573.530us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 75.360s 3053.035us 1 1 100.00
rom_volatile_raw_unlock 54.620s 2135.624us 1 1 100.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 3612.500s 17440.939us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3634.860s 18829.818us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 577.540s 5984.035us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 577.540s 5984.035us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 577.540s 5984.035us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 267.700s 4010.193us 1 1 100.00
chip_otp_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 275.080s 5932.358us 1 1 100.00
chip_sw_otp_ctrl_keys 5 5 100.00
chip_sw_flash_init 991.660s 21958.761us 1 1 100.00
chip_sw_otbn_mem_scramble 267.700s 4010.193us 1 1 100.00
chip_sw_keymgr_key_derivation 1514.840s 12716.789us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 333.090s 5193.659us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 180.860s 3621.943us 1 1 100.00
chip_sw_otp_ctrl_entropy 5 5 100.00
chip_sw_flash_init 991.660s 21958.761us 1 1 100.00
chip_sw_otbn_mem_scramble 267.700s 4010.193us 1 1 100.00
chip_sw_keymgr_key_derivation 1514.840s 12716.789us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 333.090s 5193.659us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 180.860s 3621.943us 1 1 100.00
chip_sw_otp_ctrl_program 1 1 100.00
chip_sw_lc_ctrl_transition 275.080s 5932.358us 1 1 100.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 319.080s 5035.100us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 184.810s 3124.621us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 5 6 83.33
chip_sw_otp_ctrl_lc_signals_test_unlocked0 186.100s 3018.865us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 561.200s 6874.070us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 545.770s 7023.289us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 485.760s 6022.197us 0 1 0.00
chip_sw_lc_ctrl_transition 275.080s 5932.358us 1 1 100.00
chip_prim_tl_access 228.140s 9196.565us 1 1 100.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 228.140s 9196.565us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 786.020s 7225.514us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 1 1 100.00
chip_sw_pwrmgr_full_aon_reset 283.570s 6750.014us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 906.130s 26924.454us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 274.980s 7228.819us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 0 1 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 283.350s 6858.136us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 318.720s 5883.722us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 900.550s 21876.132us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 1 2 50.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 402.670s 11035.754us 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 569.840s 9373.434us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 682.920s 9854.307us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 417.140s 5047.808us 1 1 100.00
chip_sw_pwrmgr_aon_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_full_aon_reset 283.570s 6750.014us 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 209.450s 3738.179us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 2445.440s 32389.953us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 233.260s 6363.127us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 330.220s 5300.575us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1572.690s 20711.971us 1 1 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 614.790s 8116.650us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1003.480s 12312.370us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1639.310s 27165.460us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 131.870s 3416.388us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 339.990s 5902.714us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 406.750s 9149.933us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 406.750s 9149.933us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 4 4 100.00
chip_sw_pwrmgr_all_reset_reqs 1003.480s 12312.370us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1572.690s 20711.971us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 417.140s 5047.808us 1 1 100.00
chip_sw_pwrmgr_smoketest 203.560s 5043.580us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 266.280s 4029.342us 1 1 100.00
chip_sw_rstmgr_cpu_info 0 1 0.00
chip_sw_rstmgr_cpu_info 312.870s 4820.355us 0 1 0.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 256.840s 5054.546us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 1174.680s 13452.931us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 163.060s 2908.638us 1 1 100.00
chip_sw_rstmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 339.990s 5902.714us 1 1 100.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1011.400s 7812.648us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 477.920s 5463.603us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 465.960s 4509.270us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 186.690s 2770.301us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 180.860s 3621.943us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 0 1 0.00
chip_sw_rstmgr_cpu_info 312.870s 4820.355us 0 1 0.00
chip_sw_rv_core_ibex_double_fault 0 1 0.00
chip_sw_rstmgr_cpu_info 312.870s 4820.355us 0 1 0.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 1304.810s 19859.013us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 927.480s 13538.463us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 266.280s 4029.342us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 137.490s 2659.873us 0 1 0.00
chip_rv_dm_access_after_wakeup 1 1 100.00
chip_sw_rv_dm_access_after_wakeup 360.230s 7316.224us 1 1 100.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 146.440s 3177.680us 1 1 100.00
chip_rv_dm_lc_disabled 0 1 0.00
chip_rv_dm_lc_disabled 135.510s 4444.583us 0 1 0.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 603.270s 5467.007us 1 1 100.00
chip_plic_all_irqs_10 290.600s 3581.062us 1 1 100.00
chip_plic_all_irqs_20 368.530s 4581.255us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 135.350s 3167.978us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 123.660s 2587.190us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 2990.440s 15223.450us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 542.840s 7612.645us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 208.000s 4216.950us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 239.780s 3403.776us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 170.140s 3205.366us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 333.090s 5193.659us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 368.750s 5335.597us 1 1 100.00
chip_sw_sleep_sram_ret_contents 2 2 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 350.960s 7161.842us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 488.980s 8597.934us 1 1 100.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 623.890s 9461.033us 1 1 100.00
chip_sw_sram_lc_escalation 2 2 100.00
chip_sw_all_escalation_resets 339.990s 5902.714us 1 1 100.00
chip_sw_data_integrity_escalation 388.230s 6237.617us 1 1 100.00
chip_sw_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 614.790s 8116.650us 1 1 100.00
chip_sw_sysrst_ctrl_reset 987.320s 23429.522us 1 1 100.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 144.980s 3659.808us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 209.540s 3228.985us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 313.090s 4889.684us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 1 1 100.00
chip_sw_sysrst_ctrl_reset 987.320s 23429.522us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_reset 1 1 100.00
chip_sw_sysrst_ctrl_reset 987.320s 23429.522us 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2511.350s 21187.336us 1 1 100.00
chip_sw_sysrst_ctrl_flash_wp_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2511.350s 21187.336us 1 1 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 365.620s 6898.607us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2905.430s 34954.534us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 139.400s 2964.088us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 182.550s 3454.636us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 274.550s 3584.574us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 301.810s 3630.498us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 988.490s 7840.740us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 5133.000s 31544.059us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 1761.050s 11843.831us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 151.090s 2748.098us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 256.760s 3898.768us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 70.670s 2028.824us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 11076.380s 72382.909us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 1060.240s 6303.691us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 436.650s 6145.871us 0 1 0.00
rom_e2e_jtag_debug_dev 183.150s 4027.685us 0 1 0.00
rom_e2e_jtag_debug_rma 158.440s 4036.967us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 71.450s 2488.821us 0 1 0.00
rom_e2e_jtag_inject_dev 60.630s 2443.381us 0 1 0.00
rom_e2e_jtag_inject_rma 66.420s 2317.925us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 59.259s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 1 0.00
chip_sw_clkmgr_jitter_frequency 319.340s 3860.060us 0 1 0.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 314.370s 3225.236us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 867.140s 6313.741us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 883.400s 7281.138us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 247.530s 2862.899us 1 1 100.00
chip_sw_flash_memory_protection 1 1 100.00
chip_sw_flash_ctrl_mem_protection 596.680s 5099.740us 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 76.850s 2860.303us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 190.600s 3713.470us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 1 1 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 332.200s 6946.902us 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 300.090s 5111.828us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1003.480s 12312.370us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 436.650s 6145.871us 0 1 0.00
rom_e2e_jtag_debug_dev 183.150s 4027.685us 0 1 0.00
rom_e2e_jtag_debug_rma 158.440s 4036.967us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 343.570s 4740.770us 1 1 100.00
chip_sw_plic_alerts 1 1 100.00
chip_sw_all_escalation_resets 339.990s 5902.714us 1 1 100.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 5289.610s 38314.713us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 5289.610s 38314.713us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 213.440s 3548.840us 1 1 100.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 380.720s 4903.852us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 2935.100s 19188.046us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 7 10 70.00
chip_sival_flash_info_access 215.150s 3479.797us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 403.160s 6455.946us 1 1 100.00
chip_sw_otp_ctrl_rot_auth_config 5.270s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 148.730s 2374.036us 1 1 100.00
chip_sw_otp_ctrl_descrambling 153.070s 3363.481us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 197.940s 3365.708us 0 1 0.00
chip_sw_pwrmgr_sleep_wake_5_bug 8.570s 0.000us 0 1 0.00
chip_sw_flash_ctrl_write_clear 181.530s 3141.747us 1 1 100.00
ate_bootstrap_flash_erase 6843.030s 45682.359us 1 1 100.00
ate_bootstrap_disjoint 9696.070s 84648.043us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR @ * us: (chip_sw_spi_passthrough_collision_vseq.sv:183) virtual_sequencer [chip_sw_spi_passthrough_collision_vseq] Compare mismatch
chip_sw_spi_device_pass_through_collision 73239450673647993038474358171832018180949141297892715624891832397284201943113 322
host_rsp:
-------------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------------
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_flash_ctrl_lc_rw_en 93152871930402582580198190674151641838197698914953405010207329838783573945803 309
UVM_INFO @ 3410.090510 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *
chip_sw_otp_ctrl_lc_signals_rma 28519182423298285423681615301166422452519973040954171929014526955309338010426 342
UVM_INFO @ 6022.197440 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
chip_sw_otp_ctrl_escalation 8633051849468773417420864708454743543646255741097983957718252899959737604055 316
UVM_ERROR @ 3713.470320 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3713.470320 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_csrng_fuse_en_sw_app_read_test 99494962101353374089176805182537470754863974758200146387645180229767407840111 312
UVM_ERROR @ 3015.097284 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3015.097284 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode
chip_sw_otp_ctrl_rot_auth_config 8638257241734513089725453781059299244779228276254254646309243091646028307275 282
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_lc_walkthrough_dev 71754388811430617234045350262795917057928883173848497389286988995845345724023 369
UVM_INFO @ 11199.884572 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 55994642315882866497459572901305607828235157170973680385055066905452605474881 369
UVM_INFO @ 9281.882002 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 72782474459163987466366920357372972989379164978582382595902087714990704834754 341
UVM_INFO @ 5600.629730 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *).
chip_sw_rstmgr_cpu_info 66859599861078502285883212936721482640736047305838058206280897707418324066567 333
TL item was: req: (cip_tl_seq_item@117943) { a_addr: 'h8 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1 a_opcode: 'h0 a_user: 'h259aa d_param: 'h0 d_source: 'h1 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h1f2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{}.
UVM_INFO @ 4820.355399 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 63600664789585780358596542712301930738070653408386074832710728010165527246200 217
TL item was: req: (cip_tl_seq_item@44301) { a_addr: 'h1055c a_data: 'hd3a0a95d a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2f a_opcode: 'h4 a_user: 'h186a5 d_param: 'h0 d_source: 'h2f d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2086.495973 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 55333683762409237635361370064732820359597560595623867399760542796845358604049 224
TL item was: req: (cip_tl_seq_item@32777) { a_addr: 'h1068c a_data: 'h1fcff719 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h5 a_opcode: 'h4 a_user: 'h1b644 d_param: 'h0 d_source: 'h5 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2359.414743 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))'
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 107817834803684669245562264882449090745546033943425590717457615019147713886024 327
UVM_ERROR @ 11035.754000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 11035.754000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 4087147407955619480125572831148028115976755461500792223246987841867325271933 325
UVM_ERROR @ 6858.136000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 6858.136000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 31722113744387178436841456393954610888025617696691412538177048433832838507830 332
UVM_INFO @ 34954.533673 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:382)] CHECK-fail: Expect alert *!
chip_sw_alert_test 62150357930672706435452365858051145520209956599297534933512939978734390286307 307
UVM_INFO @ 3580.450774 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
chip_sw_alert_handler_lpg_sleep_mode_alerts 41395389444221458202209487509811388547684873335966450325490296326606683041554 313
UVM_INFO @ 3395.741120 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job killed!
chip_sw_alert_handler_lpg_sleep_mode_pings 1590646371816258675315912637768808300290973315484053954538805723326669506024 None
Offending '(reset_cause == HwReq)'
chip_sw_sensor_ctrl_alert 68060457843018165916338828798688094842991147397960592549396537057577426849380 316
UVM_ERROR @ 2933.544376 us: (pwrmgr_rstreqs_sva_if.sv:98) [ASSERT FAILED] SwResetSetCause_A
UVM_INFO @ 2933.544376 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_clkmgr_jitter_frequency 96445444623080711251000782299960876415357470451461294635352676172356379554840 343
UVM_INFO @ 3860.060464 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for !get_wakeup_status()
chip_sw_pwrmgr_lowpower_cancel 56001650991595994585256360224183953069425381025597729758757037840386478661634 311
UVM_INFO @ 3365.708328 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']
chip_sw_pwrmgr_sleep_wake_5_bug 80601599545905342437059737209274665320698195894507975068776503559284035334113 None
---- STDERR ----
Another command (pid=2276675) is running. Waiting for it to complete on the server (server_pid=251271)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 111106513911341938467676169755318434582777468354024789638242078304450816847258 None
Another command (pid=409890) is running. Waiting for it to complete on the server (server_pid=251271)...
Another command (pid=441937) is running. Waiting for it to complete on the server (server_pid=251271)...
Another command (pid=445765) is running. Waiting for it to complete on the server (server_pid=251271)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Error-[NOA] Null object access
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 78063198626877081917900126542215701400371430498284844138516815548463363392336 327
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_test_unlocked0 51207882812246657578236076324975958871035983142052740082152496237055519540263 352
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_dev 99363615938629000693925712597735363362358311135229999197741885302473299124932 319
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_rma 73495840513108507306916486141141778362800615524460342401139605096614337143586 319
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 777756150366629859414071390703017485365961193797516187811857729602056436458 307
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 44697210799206272650867030563004147588240677394005768847789204273944900600649 303
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 69122036051392655502889031667857586035534764319705994230494649743702642354427 303
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_ERROR @ * us: (cip_base_vseq.sv:649) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch
chip_rv_dm_lc_disabled 8610975874197115569490436924484296954226725926050088632644857351421547438821 235
UVM_INFO @ 4444.582530 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_idle_load 40199325651543707600349341521181806538048253182490218891261194035348227817713 312
UVM_INFO @ 3923.713000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_sleep_load 21075584464231328135235675522055890366946369946377185569803761327836299260446 318
UVM_INFO @ 2989.390000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *
chip_sw_ast_clk_rst_inputs 50290985844993249164961090989967713322675831182484885109784009566971025508758 327
UVM_INFO @ 12547.094414 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(pend_req[h2d.a_source].pend == *)'
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 82002251683041707726450814383681771661571919647225473004305532966151270594826 320
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 284: tb.dut.top_earlgrey.u_rstmgr_aon.tlul_assert_device.gen_device.gen_h2d.pendingReqPerSrc_M: started at 2924827958ps failed at 2924827958ps
Offending '(pend_req[h2d.a_source].pend == 0)'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 284: tb.dut.top_earlgrey.u_rstmgr_aon.tlul_assert_device.gen_device.gen_h2d.pendingReqPerSrc_M: started at 2924967382ps failed at 2924967382ps
Offending '(pend_req[h2d.a_source].pend == 0)'
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_no_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *
rom_e2e_keymgr_init_rom_ext_no_meas 19618929124096689680604292086109860114456768072318034690903417189334731496340 319
UVM_INFO @ 16439.215266 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)'
rom_keymgr_functest 8392657394575696749216438797267354944108067278459382405838229467821285004883 327
UVM_ERROR @ 4928.119600 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 4928.119600 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---