Simulation Results: clkmgr

 
13/04/2026 19:14:24 DVSim: v1.30.1 sha: 4ae05e3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.92 %
  • code
  • 98.07 %
  • assert
  • 94.92 %
  • func
  • 85.76 %
  • line
  • 98.94 %
  • branch
  • 98.62 %
  • cond
  • 93.61 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.970s 38.405us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.170s 54.150us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 1.010s 18.135us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 6.440s 1064.978us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.490s 152.441us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.130s 20.111us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 1.010s 18.135us 1 1 100.00
clkmgr_csr_aliasing 1.490s 152.441us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.800s 39.787us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.070s 27.000us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 1.120s 72.733us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.930s 43.207us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.970s 38.405us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 3.510s 804.028us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 3.050s 750.021us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 3.510s 804.028us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 42.500s 9389.990us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 1.040s 58.237us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 3.730s 571.810us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 3.730s 571.810us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 1.170s 54.150us 1 1 100.00
clkmgr_csr_rw 1.010s 18.135us 1 1 100.00
clkmgr_csr_aliasing 1.490s 152.441us 1 1 100.00
clkmgr_same_csr_outstanding 1.180s 25.094us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 1.170s 54.150us 1 1 100.00
clkmgr_csr_rw 1.010s 18.135us 1 1 100.00
clkmgr_csr_aliasing 1.490s 152.441us 1 1 100.00
clkmgr_same_csr_outstanding 1.180s 25.094us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 1.480s 117.519us 0 1 0.00
clkmgr_tl_intg_err 2.300s 327.125us 1 1 100.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.790s 134.477us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.790s 134.477us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.790s 134.477us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.790s 134.477us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.930s 8.948us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 2.300s 327.125us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 3.510s 804.028us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 3.050s 750.021us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.790s 134.477us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.490s 122.834us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.710s 18.036us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 1.010s 44.152us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.870s 59.164us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.900s 24.493us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 1.010s 18.135us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 1.480s 117.519us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 1.010s 18.135us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 1.010s 18.135us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 1.480s 117.519us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 3.790s 1057.883us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 68.250s 11417.644us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (clkmgr_common_vseq.sv:50) [clkmgr_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault does not trigger!
clkmgr_shadow_reg_errors_with_csr_rw 56460517924198473836260313050462151725772972147392310201641896470656206104623 75
UVM_INFO @ 8947734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [clkmgr_common_vseq] expect alert:fatal_fault to fire
clkmgr_sec_cm 58427541265742303686505557741722842028028870042534659606127592776372567592932 154
UVM_INFO @ 117519434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---