Simulation Results: edn/edn0

 
13/04/2026 19:14:24 DVSim: v1.30.1 sha: 4ae05e3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.15 %
  • code
  • 77.72 %
  • assert
  • 94.36 %
  • func
  • 80.36 %
  • line
  • 96.47 %
  • branch
  • 88.15 %
  • cond
  • 84.74 %
  • toggle
  • 74.07 %
  • FSM
  • 45.16 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.140s 21.429us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.860s 32.601us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.910s 156.399us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.670s 250.153us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.320s 37.781us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.180s 45.352us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.910s 156.399us 1 1 100.00
edn_csr_aliasing 1.320s 37.781us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.120s 56.424us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.120s 56.424us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.120s 56.424us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.910s 28.674us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.070s 25.394us 1 1 100.00
errs 1 1 100.00
edn_err 0.880s 88.180us 1 1 100.00
disable 2 2 100.00
edn_disable 0.820s 61.438us 1 1 100.00
edn_disable_auto_req_mode 1.150s 174.165us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 5.250s 378.195us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.860s 23.015us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.900s 21.449us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.720s 22.657us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.720s 22.657us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.860s 32.601us 1 1 100.00
edn_csr_rw 0.910s 156.399us 1 1 100.00
edn_csr_aliasing 1.320s 37.781us 1 1 100.00
edn_same_csr_outstanding 1.210s 49.370us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.860s 32.601us 1 1 100.00
edn_csr_rw 0.910s 156.399us 1 1 100.00
edn_csr_aliasing 1.320s 37.781us 1 1 100.00
edn_same_csr_outstanding 1.210s 49.370us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 7.650s 2197.460us 1 1 100.00
edn_tl_intg_err 1.420s 54.500us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.910s 32.348us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.070s 25.394us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.650s 2197.460us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.650s 2197.460us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 7.650s 2197.460us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 7.650s 2197.460us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.070s 25.394us 1 1 100.00
edn_sec_cm 7.650s 2197.460us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.070s 25.394us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.420s 54.500us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 61.440s 14760.058us 1 1 100.00