Simulation Results: edn/edn1

 
13/04/2026 19:14:24 DVSim: v1.30.1 sha: 4ae05e3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.07 %
  • code
  • 84.19 %
  • assert
  • 97.14 %
  • func
  • 76.89 %
  • line
  • 98.18 %
  • branch
  • 93.29 %
  • cond
  • 87.08 %
  • toggle
  • 94.67 %
  • FSM
  • 47.73 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.900s 18.186us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.730s 36.876us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.760s 37.696us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.420s 202.615us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.000s 49.997us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.940s 68.753us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.760s 37.696us 1 1 100.00
edn_csr_aliasing 1.000s 49.997us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.130s 52.684us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.130s 52.684us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.130s 52.684us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.780s 32.515us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.030s 22.250us 1 1 100.00
errs 1 1 100.00
edn_err 0.830s 20.893us 1 1 100.00
disable 2 2 100.00
edn_disable 0.850s 33.579us 1 1 100.00
edn_disable_auto_req_mode 0.880s 19.314us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.280s 288.573us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.730s 22.444us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.890s 35.566us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.450s 417.039us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.450s 417.039us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.730s 36.876us 1 1 100.00
edn_csr_rw 0.760s 37.696us 1 1 100.00
edn_csr_aliasing 1.000s 49.997us 1 1 100.00
edn_same_csr_outstanding 0.910s 55.173us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.730s 36.876us 1 1 100.00
edn_csr_rw 0.760s 37.696us 1 1 100.00
edn_csr_aliasing 1.000s 49.997us 1 1 100.00
edn_same_csr_outstanding 0.910s 55.173us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.170s 141.492us 1 1 100.00
edn_tl_intg_err 1.430s 247.020us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.790s 94.260us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.030s 22.250us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.170s 141.492us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.170s 141.492us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.170s 141.492us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.170s 141.492us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.030s 22.250us 1 1 100.00
edn_sec_cm 2.170s 141.492us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.030s 22.250us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.430s 247.020us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
edn_stress_all_with_rand_reset 34.500s 2387.389us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
edn_stress_all_with_rand_reset 25277099943508966784039648587736913728793260487736875655698660311410199066165 280
UVM_INFO @ 2387389121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---