Simulation Results: flash_ctrl

 
13/04/2026 19:14:24 DVSim: v1.30.1 sha: 4ae05e3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.55 %
  • code
  • 93.74 %
  • assert
  • 96.76 %
  • func
  • 96.16 %
  • line
  • 95.94 %
  • branch
  • 97.10 %
  • cond
  • 93.45 %
  • toggle
  • 97.88 %
  • FSM
  • 84.35 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 37.470s 26.683us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 11.530s 19.343us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 13.500s 28.651us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 5.820s 61.219us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 22.710s 332.536us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 16.980s 223.288us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 9.680s 87.536us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 5.820s 61.219us 1 1 100.00
flash_ctrl_csr_aliasing 16.980s 223.288us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 13.240s 25.767us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 5.990s 22.235us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 10.800s 96.211us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 32.060s 82.805us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1365.920s 340388.964us 1 1 100.00
flash_ctrl_hw_rma_reset 614.890s 80145.475us 1 1 100.00
flash_ctrl_lcmgr_intg 9.680s 102.857us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1206.220s 360844.502us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 275.110s 13941.683us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 5.650s 175.947us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 2906.640s 50873.340us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 76.740s 7779.621us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 17.800s 29.124us 1 1 100.00
flash_ctrl_rw_evict_all_en 14.160s 64.358us 1 1 100.00
flash_ctrl_re_evict 15.880s 216.779us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 88.200s 131.444us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 88.200s 131.444us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 268.980s 26573.033us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 15.380s 2157.087us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 40.670s 62.613us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 580.930s 7500.592us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 264.040s 334.393us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 662.490s 370.099us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 8.850s 79.068us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 140.340s 3561.370us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 12.550s 53.103us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 5.510s 17.561us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 201.710s 208.969us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 59.000s 10563.178us 1 1 100.00
flash_ctrl_otp_reset 55.420s 72.131us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1365.920s 340388.964us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 148.140s 1198.993us 1 1 100.00
flash_ctrl_intr_wr 50.750s 6800.243us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 213.190s 59119.614us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 138.850s 51751.340us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 71.040s 24656.887us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 34.740s 3800.483us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 9.770s 87.726us 1 1 100.00
flash_ctrl_ro_derr 92.770s 588.552us 1 1 100.00
flash_ctrl_rw_derr 134.480s 3596.841us 1 1 100.00
flash_ctrl_derr_detect 120.530s 1678.824us 1 1 100.00
flash_ctrl_integrity 403.870s 7893.067us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 9.780s 95.422us 1 1 100.00
flash_ctrl_ro_serr 86.050s 1713.294us 1 1 100.00
flash_ctrl_rw_serr 143.480s 3027.305us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 35.080s 1893.063us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 41.110s 628.612us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 160.780s 41633.406us 1 1 100.00
flash_ctrl_write_word_sweep 6.780s 79.503us 1 1 100.00
flash_ctrl_read_word_sweep 6.080s 26.002us 1 1 100.00
flash_ctrl_ro 87.760s 2153.004us 1 1 100.00
flash_ctrl_rw 371.700s 16941.147us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 22.430s 368.722us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 654.130s 137821.658us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 29.510s 10062.884us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 6.390s 29.459us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 10.840s 17.387us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 8.630s 50.836us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 8.630s 50.836us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 13.500s 28.651us 1 1 100.00
flash_ctrl_csr_rw 5.820s 61.219us 1 1 100.00
flash_ctrl_csr_aliasing 16.980s 223.288us 1 1 100.00
flash_ctrl_same_csr_outstanding 10.740s 650.297us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 13.500s 28.651us 1 1 100.00
flash_ctrl_csr_rw 5.820s 61.219us 1 1 100.00
flash_ctrl_csr_aliasing 16.980s 223.288us 1 1 100.00
flash_ctrl_same_csr_outstanding 10.740s 650.297us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 50.180s 88.973us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 50.180s 88.973us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 50.180s 88.973us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 50.180s 88.973us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 15.420s 55.960us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_sec_cm 1531.250s 10749.393us 1 1 100.00
flash_ctrl_tl_intg_err 135.990s 211.097us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 135.990s 211.097us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 135.990s 211.097us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 12.580s 117.539us 1 1 100.00
flash_ctrl_wr_intg 6.780s 46.655us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 37.470s 26.683us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 55.420s 72.131us 1 1 100.00
flash_ctrl_disable 12.550s 53.103us 1 1 100.00
flash_ctrl_sec_info_access 49.010s 25878.555us 1 1 100.00
flash_ctrl_connect 5.510s 17.561us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 6.090s 22.958us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 5.820s 61.219us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 50.180s 88.973us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 5.820s 61.219us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 50.180s 88.973us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 5.820s 61.219us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 50.180s 88.973us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 12.550s 53.103us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 12.580s 117.539us 1 1 100.00
flash_ctrl_access_after_disable 5.640s 116.487us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 13.760s 39.868us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 12.550s 53.103us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 15.380s 2157.087us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 371.700s 16941.147us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 143.480s 3027.305us 1 1 100.00
flash_ctrl_rw_derr 134.480s 3596.841us 1 1 100.00
flash_ctrl_integrity 403.870s 7893.067us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1365.920s 340388.964us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1531.250s 10749.393us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1531.250s 10749.393us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1531.250s 10749.393us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1531.250s 10749.393us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 16.920s 733.029us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 6.730s 39.610us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 11.270s 23.128us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1531.250s 10749.393us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1531.250s 10749.393us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1531.250s 10749.393us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 21.860s 189.255us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 298.310s 1175.657us 1 1 100.00