Simulation Results: hmac

 
13/04/2026 19:14:24 DVSim: v1.30.1 sha: 4ae05e3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.07 %
  • code
  • 97.94 %
  • assert
  • 96.70 %
  • func
  • 42.57 %
  • line
  • 99.69 %
  • branch
  • 99.50 %
  • cond
  • 96.40 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 1.750s 368.019us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.790s 41.134us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.820s 109.364us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 11.260s 2148.328us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 2.650s 639.562us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.160s 32.598us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.820s 109.364us 1 1 100.00
hmac_csr_aliasing 2.650s 639.562us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 7.550s 529.058us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 71.250s 3371.021us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 8.320s 174.643us 1 1 100.00
hmac_test_sha384_vectors 19.120s 238.801us 1 1 100.00
hmac_test_sha512_vectors 309.900s 40423.615us 1 1 100.00
hmac_test_hmac256_vectors 9.550s 2483.347us 1 1 100.00
hmac_test_hmac384_vectors 5.820s 731.749us 1 1 100.00
hmac_test_hmac512_vectors 10.000s 3974.193us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 6.290s 641.223us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 281.110s 2196.200us 1 1 100.00
error 1 1 100.00
hmac_error 0.730s 17.018us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 23.820s 3356.659us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 1.750s 368.019us 1 1 100.00
hmac_long_msg 7.550s 529.058us 1 1 100.00
hmac_back_pressure 71.250s 3371.021us 1 1 100.00
hmac_datapath_stress 281.110s 2196.200us 1 1 100.00
hmac_burst_wr 6.290s 641.223us 1 1 100.00
hmac_stress_all 1670.890s 39493.376us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 1.750s 368.019us 1 1 100.00
hmac_long_msg 7.550s 529.058us 1 1 100.00
hmac_back_pressure 71.250s 3371.021us 1 1 100.00
hmac_datapath_stress 281.110s 2196.200us 1 1 100.00
hmac_wipe_secret 23.820s 3356.659us 1 1 100.00
hmac_test_sha256_vectors 8.320s 174.643us 1 1 100.00
hmac_test_sha384_vectors 19.120s 238.801us 1 1 100.00
hmac_test_sha512_vectors 309.900s 40423.615us 1 1 100.00
hmac_test_hmac256_vectors 9.550s 2483.347us 1 1 100.00
hmac_test_hmac384_vectors 5.820s 731.749us 1 1 100.00
hmac_test_hmac512_vectors 10.000s 3974.193us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 1.750s 368.019us 1 1 100.00
hmac_long_msg 7.550s 529.058us 1 1 100.00
hmac_back_pressure 71.250s 3371.021us 1 1 100.00
hmac_datapath_stress 281.110s 2196.200us 1 1 100.00
hmac_burst_wr 6.290s 641.223us 1 1 100.00
hmac_error 0.730s 17.018us 1 1 100.00
hmac_wipe_secret 23.820s 3356.659us 1 1 100.00
hmac_test_sha256_vectors 8.320s 174.643us 1 1 100.00
hmac_test_sha384_vectors 19.120s 238.801us 1 1 100.00
hmac_test_sha512_vectors 309.900s 40423.615us 1 1 100.00
hmac_test_hmac256_vectors 9.550s 2483.347us 1 1 100.00
hmac_test_hmac384_vectors 5.820s 731.749us 1 1 100.00
hmac_test_hmac512_vectors 10.000s 3974.193us 1 1 100.00
hmac_stress_all 1670.890s 39493.376us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 1670.890s 39493.376us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.610s 31.402us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.600s 111.647us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 1.630s 95.762us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 1.630s 95.762us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.790s 41.134us 1 1 100.00
hmac_csr_rw 0.820s 109.364us 1 1 100.00
hmac_csr_aliasing 2.650s 639.562us 1 1 100.00
hmac_same_csr_outstanding 1.510s 267.456us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.790s 41.134us 1 1 100.00
hmac_csr_rw 0.820s 109.364us 1 1 100.00
hmac_csr_aliasing 2.650s 639.562us 1 1 100.00
hmac_same_csr_outstanding 1.510s 267.456us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.830s 98.615us 1 1 100.00
hmac_tl_intg_err 2.880s 153.730us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.880s 153.730us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 1.750s 368.019us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 3.580s 165.399us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 55.650s 1749.227us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 5.110s 2283.873us 1 1 100.00