Simulation Results

Simulation Results: i2c

13/04/2026 19:14:24 DVSim: v1.30.1 sha: 4ae05e3 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
85.41 %

code
81.49 %

assert
96.19 %

func
78.54 %

line
96.38 %

branch
92.41 %

cond
84.97 %

toggle
89.66 %

FSM
44.05 %

Validation stages

V1		100.00%
V2		90.24%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	32.520s	5838.072us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	7.960s	3205.374us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.740s	67.414us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.700s	69.800us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	1.970s	66.145us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.180s	270.448us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	0.970s	163.040us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.700s	69.800us	1	1	100.00
	i2c_csr_aliasing	1.180s	270.448us	1	1	100.00

37/41 passed

90.24 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	0.790s	21.105us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	254.740s	123710.022us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	43.890s	2476.042us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.820s	20.089us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	234.300s	26397.884us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	31.430s	3314.768us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	0.990s	306.654us	1	1	100.00
	i2c_host_fifo_fmt_empty	13.030s	1430.820us	1	1	100.00
	i2c_host_fifo_reset_rx	7.440s	831.784us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	96.140s	10588.840us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	15.610s	2379.256us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	0.850s	31.091us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	1.980s	422.444us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	52.000s	40322.247us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	3.320s	2270.056us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	20.060s	6428.659us	1	1	100.00
	i2c_target_intr_smoke	3.150s	2782.907us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	1.130s	1209.586us	1	1	100.00
	i2c_target_fifo_reset_tx	0.790s	294.664us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	89.910s	37274.777us	1	1	100.00
	i2c_target_stress_rd	20.060s	6428.659us	1	1	100.00
	i2c_target_intr_stress_wr	5.320s	23248.610us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	3.990s	1146.045us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	2.690s	326.419us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	3.410s	1088.338us	1	1	100.00
target_mode_glitch				1	1	100.00
	i2c_target_hrst	1.620s	215.508us	1	1	100.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	1.940s	1493.056us	1	1	100.00
	i2c_target_fifo_watermarks_tx	1.300s	618.419us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	43.890s	2476.042us	1	1	100.00
	i2c_host_perf_precise	3.270s	150.743us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	15.610s	2379.256us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	2.240s	120.203us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	2.300s	4221.347us	1	1	100.00
	i2c_target_nack_acqfull_addr	1.870s	6583.720us	1	1	100.00
	i2c_target_nack_txstretch	1.350s	291.299us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	9.960s	320.758us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	2.140s	982.204us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.770s	16.013us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.770s	43.849us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	1.330s	259.080us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	1.330s	259.080us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.740s	67.414us	1	1	100.00
	i2c_csr_rw	0.700s	69.800us	1	1	100.00
	i2c_csr_aliasing	1.180s	270.448us	1	1	100.00
	i2c_same_csr_outstanding	0.990s	21.100us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.740s	67.414us	1	1	100.00
	i2c_csr_rw	0.700s	69.800us	1	1	100.00
	i2c_csr_aliasing	1.180s	270.448us	1	1	100.00
	i2c_same_csr_outstanding	0.990s	21.100us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	1.220s	173.383us	1	1	100.00
	i2c_sec_cm	0.970s	46.400us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.220s	173.383us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	5.260s	412.707us	1
target_error_intr				1
	i2c_target_unexp_stop	1.330s	587.779us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	14.860s	1076.718us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
	i2c_host_error_intr	21351375992154220235166139222187526095568085529955305320203695223778939386234	86	UVM_INFO @ 21104902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_mode_toggle	104404992942394348134913983013555160767793896477528286121821482737127778956058	81	UVM_INFO @ 31090549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared:
	i2c_host_stress_all	19690021437262939783923065315120099857570472899813336620887809933103722168987	139	---------------------------------------------------- Name Type Size Value ---------------------------------------------------- mon_dut_item i2c_item - @3197220
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
	i2c_target_glitch	84897350771364958388051576287187452181252685419005903750601250966087786374368	84	UVM_INFO @ 422444412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])
	i2c_target_unexp_stop	76678138376304674872638477672018444234868524980813241358208370221373817290824	78	UVM_INFO @ 587779389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
	i2c_host_stress_all_with_rand_reset	91961453508097290730418365813078857894006467099172790327576446893717601566135	103	UVM_INFO @ 412706611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1149) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses \|\| !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
	i2c_target_stress_all_with_rand_reset	2983136590360833837251571820763156734386378292051964545888608167717968664434	90	UVM_INFO @ 1076718059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---