Simulation Results: lc_ctrl/volatile_unlock_disabled

 
13/04/2026 19:14:24 DVSim: v1.30.1 sha: 4ae05e3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.69 %
  • code
  • 84.45 %
  • assert
  • 93.85 %
  • func
  • 93.77 %
  • line
  • 97.17 %
  • branch
  • 93.97 %
  • cond
  • 78.95 %
  • toggle
  • 88.62 %
  • FSM
  • 63.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.410s 57.524us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.810s 19.507us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.950s 26.716us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.090s 172.165us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.020s 26.967us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.040s 36.208us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.950s 26.716us 1 1 100.00
lc_ctrl_csr_aliasing 1.020s 26.967us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.030s 76.770us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 6.690s 1145.974us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.100s 23.152us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.560s 143.388us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 8.000s 254.904us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.240s 1897.158us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 8.000s 254.904us 1 1 100.00
lc_ctrl_prog_failure 2.560s 143.388us 1 1 100.00
lc_ctrl_errors 5.240s 1897.158us 1 1 100.00
lc_ctrl_security_escalation 7.590s 1853.752us 1 1 100.00
lc_ctrl_jtag_state_failure 15.310s 1736.845us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.120s 241.855us 1 1 100.00
lc_ctrl_jtag_errors 18.660s 7254.451us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 6.970s 1505.460us 1 1 100.00
lc_ctrl_jtag_state_post_trans 11.990s 1666.699us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.120s 241.855us 1 1 100.00
lc_ctrl_jtag_errors 18.660s 7254.451us 1 1 100.00
lc_ctrl_jtag_access 2.040s 591.198us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 17.820s 3470.820us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.390s 460.687us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.340s 434.855us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 3.410s 401.498us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 7.440s 2255.080us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.240s 69.602us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.030s 422.867us 1 1 100.00
lc_ctrl_jtag_alert_test 1.060s 111.873us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 10.440s 1221.530us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.030s 40.786us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 129.910s 10329.987us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.840s 18.053us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.310s 103.560us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.310s 103.560us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.810s 19.507us 1 1 100.00
lc_ctrl_csr_rw 0.950s 26.716us 1 1 100.00
lc_ctrl_csr_aliasing 1.020s 26.967us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.380s 46.199us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.810s 19.507us 1 1 100.00
lc_ctrl_csr_rw 0.950s 26.716us 1 1 100.00
lc_ctrl_csr_aliasing 1.020s 26.967us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.380s 46.199us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 7.630s 834.258us 1 1 100.00
lc_ctrl_tl_intg_err 2.360s 80.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.360s 80.000us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 6.690s 1145.974us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 8.000s 254.904us 1 1 100.00
lc_ctrl_sec_cm 7.630s 834.258us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 8.000s 254.904us 1 1 100.00
lc_ctrl_sec_cm 7.630s 834.258us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.000s 254.904us 1 1 100.00
lc_ctrl_sec_cm 7.630s 834.258us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.000s 254.904us 1 1 100.00
lc_ctrl_sec_cm 7.630s 834.258us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 8.000s 254.904us 1 1 100.00
lc_ctrl_sec_cm 7.630s 834.258us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.000s 254.904us 1 1 100.00
lc_ctrl_sec_cm 7.630s 834.258us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.000s 254.904us 1 1 100.00
lc_ctrl_sec_cm 7.630s 834.258us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 8.000s 254.904us 1 1 100.00
lc_ctrl_sec_cm 7.630s 834.258us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 7.590s 1853.752us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.030s 76.770us 1 1 100.00
lc_ctrl_jtag_state_post_trans 11.990s 1666.699us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 8.110s 551.206us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 8.110s 551.206us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.490s 344.648us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 11.480s 5917.533us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 11.480s 5917.533us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 37.800s 6051.199us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 36135816718838642339921286320474411303581841498036437527023604253344893504754 6012
UVM_INFO @ 6051198691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---