Simulation Results: lc_ctrl/volatile_unlock_enabled

 
13/04/2026 19:14:24 DVSim: v1.30.1 sha: 4ae05e3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.60 %
  • code
  • 84.24 %
  • assert
  • 94.13 %
  • func
  • 93.42 %
  • line
  • 97.10 %
  • branch
  • 93.62 %
  • cond
  • 79.01 %
  • toggle
  • 86.06 %
  • FSM
  • 65.42 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.510s 193.289us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.810s 53.211us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.910s 15.797us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.440s 29.878us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.090s 82.244us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.950s 122.361us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.910s 15.797us 1 1 100.00
lc_ctrl_csr_aliasing 1.090s 82.244us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.370s 618.740us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 4.090s 1367.696us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.790s 33.805us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.970s 192.044us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 11.250s 277.590us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 6.920s 312.060us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 11.250s 277.590us 1 1 100.00
lc_ctrl_prog_failure 1.970s 192.044us 1 1 100.00
lc_ctrl_errors 6.920s 312.060us 1 1 100.00
lc_ctrl_security_escalation 7.310s 1205.207us 1 1 100.00
lc_ctrl_jtag_state_failure 17.920s 1268.340us 1 1 100.00
lc_ctrl_jtag_prog_failure 5.540s 543.573us 1 1 100.00
lc_ctrl_jtag_errors 12.320s 2074.495us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 1.200s 123.730us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.510s 1606.946us 1 1 100.00
lc_ctrl_jtag_prog_failure 5.540s 543.573us 1 1 100.00
lc_ctrl_jtag_errors 12.320s 2074.495us 1 1 100.00
lc_ctrl_jtag_access 6.590s 970.832us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 19.560s 943.582us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.050s 150.927us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.220s 136.170us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 6.800s 7217.115us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.510s 433.363us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.310s 21.670us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.920s 1981.062us 1 1 100.00
lc_ctrl_jtag_alert_test 1.440s 39.627us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.550s 437.455us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.870s 23.112us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 45.000s 18519.889us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.020s 66.712us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.170s 34.451us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.170s 34.451us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.810s 53.211us 1 1 100.00
lc_ctrl_csr_rw 0.910s 15.797us 1 1 100.00
lc_ctrl_csr_aliasing 1.090s 82.244us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.390s 86.492us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.810s 53.211us 1 1 100.00
lc_ctrl_csr_rw 0.910s 15.797us 1 1 100.00
lc_ctrl_csr_aliasing 1.090s 82.244us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.390s 86.492us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 8.210s 261.053us 1 1 100.00
lc_ctrl_tl_intg_err 2.070s 111.547us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.070s 111.547us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 4.090s 1367.696us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 11.250s 277.590us 1 1 100.00
lc_ctrl_sec_cm 8.210s 261.053us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 11.250s 277.590us 1 1 100.00
lc_ctrl_sec_cm 8.210s 261.053us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 11.250s 277.590us 1 1 100.00
lc_ctrl_sec_cm 8.210s 261.053us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 11.250s 277.590us 1 1 100.00
lc_ctrl_sec_cm 8.210s 261.053us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 11.250s 277.590us 1 1 100.00
lc_ctrl_sec_cm 8.210s 261.053us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 11.250s 277.590us 1 1 100.00
lc_ctrl_sec_cm 8.210s 261.053us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 11.250s 277.590us 1 1 100.00
lc_ctrl_sec_cm 8.210s 261.053us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 11.250s 277.590us 1 1 100.00
lc_ctrl_sec_cm 8.210s 261.053us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 7.310s 1205.207us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.370s 618.740us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.510s 1606.946us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.100s 1004.098us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.100s 1004.098us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 6.620s 408.968us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.570s 245.606us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.570s 245.606us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 46.980s 27964.468us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 52354037120740936204319816676235291481148585958658051494285318096954795384642 1676
UVM_INFO @ 27964468138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---