Simulation Results: otp_ctrl

 
13/04/2026 19:14:24 DVSim: v1.30.1 sha: 4ae05e3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 80.22 %
  • code
  • 78.00 %
  • assert
  • 92.00 %
  • func
  • 70.66 %
  • line
  • 88.50 %
  • branch
  • 81.85 %
  • cond
  • 89.50 %
  • toggle
  • 85.70 %
  • FSM
  • 44.44 %
Validation stages
V1
100.00%
V2
85.00%
V2S
77.78%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.510s 109.871us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 4.040s 183.975us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.430s 109.309us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.840s 663.940us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 4.280s 1199.297us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 5.080s 261.235us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.850s 106.930us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.840s 663.940us 1 1 100.00
otp_ctrl_csr_aliasing 5.080s 261.235us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.190s 136.594us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.260s 76.184us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 12.090s 616.157us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 2.900s 278.384us 1 1 100.00
partition_check 1 2 50.00
otp_ctrl_background_chks 23.170s 5881.647us 0 1 0.00
otp_ctrl_check_fail 6.810s 869.065us 1 1 100.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 3.960s 1978.903us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 11.500s 644.901us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 6.450s 3924.401us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 14.200s 5676.813us 1 1 100.00
otp_ctrl_parallel_lc_esc 18.200s 2341.648us 1 1 100.00
otp_dai_errors 0 1 0.00
otp_ctrl_dai_errs 1.480s 125.438us 0 1 0.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 1.890s 142.853us 0 1 0.00
test_access 1 1 100.00
otp_ctrl_test_access 11.620s 3505.131us 1 1 100.00
stress_all 1 1 100.00
otp_ctrl_stress_all 92.240s 15247.296us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.450s 543.390us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.370s 47.010us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 4.630s 1290.672us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 4.630s 1290.672us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.430s 109.309us 1 1 100.00
otp_ctrl_csr_rw 1.840s 663.940us 1 1 100.00
otp_ctrl_csr_aliasing 5.080s 261.235us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.060s 110.681us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.430s 109.309us 1 1 100.00
otp_ctrl_csr_rw 1.840s 663.940us 1 1 100.00
otp_ctrl_csr_aliasing 5.080s 261.235us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.060s 110.681us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 0 1 0.00
otp_ctrl_sec_cm 33.880s 29146.833us 0 1 0.00
tl_intg_err 1 2 50.00
otp_ctrl_sec_cm 33.880s 29146.833us 0 1 0.00
otp_ctrl_tl_intg_err 6.560s 2460.337us 1 1 100.00
prim_count_check 0 1 0.00
otp_ctrl_sec_cm 33.880s 29146.833us 0 1 0.00
prim_fsm_check 0 1 0.00
otp_ctrl_sec_cm 33.880s 29146.833us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 6.560s 2460.337us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 4.040s 183.975us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 4.040s 183.975us 1 1 100.00
sec_cm_dai_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 33.880s 29146.833us 0 1 0.00
sec_cm_kdi_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 33.880s 29146.833us 0 1 0.00
sec_cm_lci_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 33.880s 29146.833us 0 1 0.00
sec_cm_part_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 33.880s 29146.833us 0 1 0.00
sec_cm_scrmbl_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 33.880s 29146.833us 0 1 0.00
sec_cm_timer_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 33.880s 29146.833us 0 1 0.00
sec_cm_dai_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 33.880s 29146.833us 0 1 0.00
sec_cm_kdi_seed_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 33.880s 29146.833us 0 1 0.00
sec_cm_kdi_entropy_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 33.880s 29146.833us 0 1 0.00
sec_cm_lci_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 33.880s 29146.833us 0 1 0.00
sec_cm_part_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 33.880s 29146.833us 0 1 0.00
sec_cm_scrmbl_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 33.880s 29146.833us 0 1 0.00
sec_cm_timer_integ_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 33.880s 29146.833us 0 1 0.00
sec_cm_timer_cnsty_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 33.880s 29146.833us 0 1 0.00
sec_cm_timer_lfsr_redun 0 1 0.00
otp_ctrl_sec_cm 33.880s 29146.833us 0 1 0.00
sec_cm_dai_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 18.200s 2341.648us 1 1 100.00
otp_ctrl_sec_cm 33.880s 29146.833us 0 1 0.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 18.200s 2341.648us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 18.200s 2341.648us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 18.200s 2341.648us 1 1 100.00
otp_ctrl_macro_errs 1.890s 142.853us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 18.200s 2341.648us 1 1 100.00
sec_cm_timer_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 18.200s 2341.648us 1 1 100.00
otp_ctrl_sec_cm 33.880s 29146.833us 0 1 0.00
sec_cm_dai_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 18.200s 2341.648us 1 1 100.00
otp_ctrl_sec_cm 33.880s 29146.833us 0 1 0.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 18.200s 2341.648us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 18.200s 2341.648us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 18.200s 2341.648us 1 1 100.00
otp_ctrl_macro_errs 1.890s 142.853us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 18.200s 2341.648us 1 1 100.00
sec_cm_timer_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 18.200s 2341.648us 1 1 100.00
otp_ctrl_sec_cm 33.880s 29146.833us 0 1 0.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 2.900s 278.384us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 1 1 100.00
otp_ctrl_check_fail 6.810s 869.065us 1 1 100.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 11.500s 644.901us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 11.500s 644.901us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 11.500s 644.901us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 11.500s 644.901us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 11.500s 644.901us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 4.040s 183.975us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 11.500s 644.901us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 4.040s 183.975us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 33.880s 29146.833us 0 1 0.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 3.960s 1978.903us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 4.040s 183.975us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 4.040s 183.975us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 1.890s 142.853us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 8.690s 3061.607us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 11.270s 8335.445us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1315) [otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_check_error does not trigger!
otp_ctrl_background_chks 43289702511438158324753379808428310354394359430077217801655506961821749099812 13672
UVM_INFO @ 5881646869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_*
otp_ctrl_dai_errs 96598752971120038632965911408145227898671115540891888079629673861654583565337 517
UVM_INFO @ 125438141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert fatal_macro_error did not trigger max_delay:*
otp_ctrl_macro_errs 52288422897948750013698888151064642098127956730823946196627482617774182718212 877
UVM_INFO @ 142853225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = *
otp_ctrl_stress_all_with_rand_reset 73427080168246694434834884901429515954892971234159471062181539125121404914637 804
UVM_INFO @ 8335444811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [otp_ctrl_common_vseq] expect alert:fatal_check_error to fire
otp_ctrl_sec_cm 15697426863892385677666240701043385131983959260863054227677675117025972878820 567
UVM_INFO @ 29146832551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---