Simulation Results: pattgen

 
13/04/2026 19:14:24 DVSim: v1.30.1 sha: 4ae05e3 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.08 %
  • code
  • 98.87 %
  • assert
  • 96.95 %
  • func
  • 89.42 %
  • block
  • 100.00 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • toggle
  • 96.61 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
0.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pattgen_smoke 2.000s 26.398us 1 1 100.00
csr_hw_reset 1 1 100.00
pattgen_csr_hw_reset 1.000s 50.205us 1 1 100.00
csr_rw 1 1 100.00
pattgen_csr_rw 1.000s 46.236us 1 1 100.00
csr_bit_bash 1 1 100.00
pattgen_csr_bit_bash 3.000s 590.115us 1 1 100.00
csr_aliasing 1 1 100.00
pattgen_csr_aliasing 2.000s 31.140us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pattgen_csr_mem_rw_with_rand_reset 2.000s 22.549us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pattgen_csr_rw 1.000s 46.236us 1 1 100.00
pattgen_csr_aliasing 2.000s 31.140us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
perf 1 1 100.00
pattgen_perf 11.000s 1402.559us 1 1 100.00
cnt_rollover 1 1 100.00
cnt_rollover 15.000s 2312.405us 1 1 100.00
error 1 1 100.00
pattgen_error 1.000s 40.879us 1 1 100.00
stress_all 0 1 0.00
pattgen_stress_all 10656.000s 5847958.000us 0 1 0.00
alert_test 1 1 100.00
pattgen_alert_test 1.000s 16.140us 1 1 100.00
intr_test 1 1 100.00
pattgen_intr_test 1.000s 17.113us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pattgen_tl_errors 2.000s 162.159us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pattgen_tl_errors 2.000s 162.159us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 50.205us 1 1 100.00
pattgen_csr_rw 1.000s 46.236us 1 1 100.00
pattgen_csr_aliasing 2.000s 31.140us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 16.414us 1 1 100.00
tl_d_partial_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 50.205us 1 1 100.00
pattgen_csr_rw 1.000s 46.236us 1 1 100.00
pattgen_csr_aliasing 2.000s 31.140us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 16.414us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pattgen_tl_intg_err 1.000s 189.541us 1 1 100.00
pattgen_sec_cm 2.000s 291.304us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pattgen_tl_intg_err 1.000s 189.541us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
pattgen_stress_all_with_rand_reset 41.000s 20002.199us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
pattgen_inactive_level 21.000s 10289.937us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15)
pattgen_inactive_level 27477199229706041699183540546680951250679934251639933553573207896133809290947 99
UVM_INFO @ 10289936514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
pattgen_stress_all_with_rand_reset 29030732187566263353804447928187126734218967415609209578181033887141650177280 149
UVM_ERROR @ 3401282028 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 3401282028 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 3401882028 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared:
pattgen_stress_all 44744248890694722869405162188051254869363140916791307621301281094783793166083 148
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10100