Simulation Results: pwrmgr

 
13/04/2026 19:14:24 DVSim: v1.30.1 sha: 4ae05e3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.74 %
  • code
  • 94.60 %
  • assert
  • 96.08 %
  • func
  • 96.54 %
  • line
  • 98.92 %
  • branch
  • 95.42 %
  • cond
  • 94.63 %
  • toggle
  • 90.02 %
  • FSM
  • 94.00 %
Validation stages
V1
100.00%
V2
93.33%
V2S
80.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.740s 29.304us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.680s 41.811us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.680s 20.005us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.600s 627.920us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.980s 49.299us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.960s 62.316us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.680s 20.005us 1 1 100.00
pwrmgr_csr_aliasing 0.980s 49.299us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.980s 207.642us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.980s 207.642us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 1.010s 57.097us 1 1 100.00
pwrmgr_lowpower_invalid 0.720s 44.802us 1 1 100.00
reset 2 2 100.00
pwrmgr_reset 0.830s 45.612us 1 1 100.00
pwrmgr_reset_invalid 0.720s 143.468us 1 1 100.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.830s 45.612us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 1.000s 242.821us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.800s 283.797us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.900s 143.104us 1 1 100.00
stress_all 0 1 0.00
pwrmgr_stress_all 4.550s 10153.432us 0 1 0.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.590s 67.149us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.870s 349.684us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.870s 349.684us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.680s 41.811us 1 1 100.00
pwrmgr_csr_rw 0.680s 20.005us 1 1 100.00
pwrmgr_csr_aliasing 0.980s 49.299us 1 1 100.00
pwrmgr_same_csr_outstanding 0.660s 66.353us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.680s 41.811us 1 1 100.00
pwrmgr_csr_rw 0.680s 20.005us 1 1 100.00
pwrmgr_csr_aliasing 0.980s 49.299us 1 1 100.00
pwrmgr_same_csr_outstanding 0.660s 66.353us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
pwrmgr_tl_intg_err 0.610s 8.672us 0 1 0.00
pwrmgr_sec_cm 0.680s 57.821us 0 1 0.00
prim_count_check 0 1 0.00
pwrmgr_sec_cm 0.680s 57.821us 0 1 0.00
prim_fsm_check 0 1 0.00
pwrmgr_sec_cm 0.680s 57.821us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
pwrmgr_tl_intg_err 0.610s 8.672us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.800s 863.611us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 1 1 100.00
pwrmgr_wakeup_reset 1.000s 242.821us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.700s 71.315us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.680s 29.729us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 0 1 0.00
pwrmgr_sec_cm 0.680s 57.821us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
pwrmgr_sec_cm 0.680s 57.821us 0 1 0.00
sec_cm_fsm_terminal 0 1 0.00
pwrmgr_sec_cm 0.680s 57.821us 0 1 0.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.630s 25.655us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.720s 40.354us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.760s 110.793us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.680s 20.005us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.680s 20.005us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 0 1 0.00
pwrmgr_escalation_timeout 0.770s 103.021us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 8.650s 5433.126us 1 1 100.00

Error Messages

   Test seed line log context
Offending '((!clk_en) || status)'
pwrmgr_escalation_timeout 56653785092608917946477822259406489644901076469442169958996507968791034245957 79
UVM_ERROR @ 103020721 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 103020721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [pwrmgr_common_vseq] expect alert:fatal_fault to fire
pwrmgr_tl_intg_err 81026085108227134449531334470294465065074715609833319149006366823316490416397 82
UVM_INFO @ 8671947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_sec_cm 62646810236329374816923967215005674793983735253221150712330551527354934982522 81
UVM_INFO @ 57821376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_vseq.sv:62) [pwrmgr_reset_vseq] wait timeout occurred!
pwrmgr_stress_all 124736779952637690254279672421209350431231998795875622829721774526220731798 169
UVM_INFO @ 10153432174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---