Simulation Results: rom_ctrl/64kb

 
13/04/2026 19:14:24 DVSim: v1.30.1 sha: 4ae05e3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.34 %
  • code
  • 99.28 %
  • assert
  • 96.80 %
  • func
  • 95.94 %
  • line
  • 99.59 %
  • branch
  • 99.27 %
  • cond
  • 97.77 %
  • toggle
  • 99.75 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 7.450s 787.457us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 10.850s 1044.039us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 6.730s 1212.727us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 10.010s 1998.277us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 5.840s 2786.524us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 7.470s 1058.521us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 6.730s 1212.727us 1 1 100.00
rom_ctrl_csr_aliasing 5.840s 2786.524us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 5.520s 1688.116us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 9.140s 1049.452us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 6.460s 659.084us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 32.150s 1109.134us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 12.520s 1482.716us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 7.010s 300.832us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 9.770s 1339.125us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 9.770s 1339.125us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 10.850s 1044.039us 1 1 100.00
rom_ctrl_csr_rw 6.730s 1212.727us 1 1 100.00
rom_ctrl_csr_aliasing 5.840s 2786.524us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.500s 1065.549us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 10.850s 1044.039us 1 1 100.00
rom_ctrl_csr_rw 6.730s 1212.727us 1 1 100.00
rom_ctrl_csr_aliasing 5.840s 2786.524us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.500s 1065.549us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 115.840s 6435.552us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 34.350s 3722.295us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 229.580s 1661.156us 1 1 100.00
rom_ctrl_tl_intg_err 51.130s 1150.288us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 229.580s 1661.156us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 229.580s 1661.156us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 115.840s 6435.552us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 115.840s 6435.552us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 115.840s 6435.552us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 115.840s 6435.552us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 115.840s 6435.552us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 229.580s 1661.156us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 229.580s 1661.156us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 7.450s 787.457us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 7.450s 787.457us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 7.450s 787.457us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 51.130s 1150.288us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 115.840s 6435.552us 1 1 100.00
rom_ctrl_kmac_err_chk 12.520s 1482.716us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 115.840s 6435.552us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 115.840s 6435.552us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 115.840s 6435.552us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 34.350s 3722.295us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 229.580s 1661.156us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 245.810s 17491.028us 1 1 100.00