Simulation Results: rstmgr

 
13/04/2026 19:14:24 DVSim: v1.30.1 sha: 4ae05e3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.10 %
  • code
  • 99.31 %
  • assert
  • 97.99 %
  • func
  • 97.01 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.40 %
  • toggle
  • 99.50 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.180s 125.402us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.150s 152.649us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.920s 68.578us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 4.020s 1039.325us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.960s 340.701us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.080s 117.538us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.920s 68.578us 1 1 100.00
rstmgr_csr_aliasing 1.960s 340.701us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.890s 230.944us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.380s 130.779us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.860s 91.500us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 3.620s 1203.744us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 3.620s 1203.744us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 3.620s 1203.744us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 3.620s 1203.744us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 17.650s 5604.863us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.780s 108.739us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.080s 354.203us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.080s 354.203us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.150s 152.649us 1 1 100.00
rstmgr_csr_rw 0.920s 68.578us 1 1 100.00
rstmgr_csr_aliasing 1.960s 340.701us 1 1 100.00
rstmgr_same_csr_outstanding 0.970s 121.244us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.150s 152.649us 1 1 100.00
rstmgr_csr_rw 0.920s 68.578us 1 1 100.00
rstmgr_csr_aliasing 1.960s 340.701us 1 1 100.00
rstmgr_same_csr_outstanding 0.970s 121.244us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 20.040s 16947.337us 1 1 100.00
rstmgr_tl_intg_err 1.630s 450.988us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 20.040s 16947.337us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 20.040s 16947.337us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 1.630s 450.988us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 0.990s 135.737us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 6.420s 2462.582us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.240s 301.910us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 20.040s 16947.337us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.920s 68.578us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.920s 68.578us 1 1 100.00