Simulation Results: rv_timer

 
13/04/2026 19:14:24 DVSim: v1.30.1 sha: 4ae05e3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.84 %
  • code
  • 99.77 %
  • assert
  • 96.82 %
  • func
  • 87.94 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 99.08 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.690s 82.310us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.700s 93.677us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.670s 11.732us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.760s 1469.589us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.760s 25.133us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.770s 67.807us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.670s 11.732us 1 1 100.00
rv_timer_csr_aliasing 0.760s 25.133us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.700s 448.449us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 1.000s 2791.479us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 44.780s 70988.762us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 44.780s 70988.762us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 6.380s 12710.871us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.630s 14.072us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.650s 27.758us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 2.080s 154.109us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 2.080s 154.109us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.700s 93.677us 1 1 100.00
rv_timer_csr_rw 0.670s 11.732us 1 1 100.00
rv_timer_csr_aliasing 0.760s 25.133us 1 1 100.00
rv_timer_same_csr_outstanding 0.720s 121.605us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.700s 93.677us 1 1 100.00
rv_timer_csr_rw 0.670s 11.732us 1 1 100.00
rv_timer_csr_aliasing 0.760s 25.133us 1 1 100.00
rv_timer_same_csr_outstanding 0.720s 121.605us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.730s 141.340us 1 1 100.00
rv_timer_tl_intg_err 1.260s 425.065us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.260s 425.065us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 1.020s 124.554us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.780s 176.602us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
rv_timer_stress_all_with_rand_reset 0.700s 10.579us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == *
rv_timer_min 81188762249282823047214725808589773224821723171054612068704455138497382026749 78
UVM_INFO @ 124553814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 33472086327560579740024869451752334332844649801312250072742036072404904382752 75
UVM_INFO @ 448448627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*])
rv_timer_max 22223523472589483999993542847767102796041247382361031295770469698582820842508 76
UVM_INFO @ 176601504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
rv_timer_stress_all_with_rand_reset 2532279383300647130684412041633242243565322325993066546995958444503981497597 79
UVM_INFO @ 10579274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---