Simulation Results: spi_device/1r1w

 
13/04/2026 19:14:24 DVSim: v1.30.1 sha: 4ae05e3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.61 %
  • code
  • 93.23 %
  • assert
  • 94.64 %
  • func
  • 59.97 %
  • line
  • 99.01 %
  • branch
  • 98.18 %
  • cond
  • 96.05 %
  • toggle
  • 83.54 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
92.31%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 179.340s 37218.508us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 0.840s 36.683us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.640s 79.975us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 28.280s 10803.094us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 10.800s 3022.765us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.730s 584.929us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.640s 79.975us 1 1 100.00
spi_device_csr_aliasing 10.800s 3022.765us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.720s 16.402us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.160s 61.734us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.960s 13.628us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.810s 2.542us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.890s 6.836us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 0.830s 282.242us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 0.830s 282.242us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 4.080s 825.609us 1 1 100.00
spi_device_tpm_sts_read 1.070s 130.458us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 19.470s 43420.097us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 14.790s 8176.226us 1 1 100.00
spi_device_flash_all 24.260s 3792.876us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 10.650s 6653.782us 1 1 100.00
spi_device_flash_all 24.260s 3792.876us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 10.650s 6653.782us 1 1 100.00
spi_device_flash_all 24.260s 3792.876us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 24.260s 3792.876us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 2.430s 29.735us 1 1 100.00
spi_device_flash_all 24.260s 3792.876us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 2.430s 29.735us 1 1 100.00
spi_device_flash_all 24.260s 3792.876us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 2.430s 29.735us 1 1 100.00
spi_device_flash_all 24.260s 3792.876us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 2.430s 29.735us 1 1 100.00
spi_device_flash_all 24.260s 3792.876us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 2.430s 29.735us 1 1 100.00
spi_device_flash_all 24.260s 3792.876us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 3.320s 728.023us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 31.870s 12264.198us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 31.870s 12264.198us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 31.870s 12264.198us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 5.610s 542.659us 1 1 100.00
spi_device_read_buffer_direct 5.910s 1005.463us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 31.870s 12264.198us 1 1 100.00
spi_device_flash_all 24.260s 3792.876us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 24.260s 3792.876us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 24.260s 3792.876us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 2.530s 538.362us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 2.530s 538.362us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 179.340s 37218.508us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 134.020s 72728.572us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 14.490s 9773.996us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.800s 44.998us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.780s 33.030us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 3.630s 418.751us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 3.630s 418.751us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 0.840s 36.683us 1 1 100.00
spi_device_csr_rw 1.640s 79.975us 1 1 100.00
spi_device_csr_aliasing 10.800s 3022.765us 1 1 100.00
spi_device_same_csr_outstanding 3.620s 224.388us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 0.840s 36.683us 1 1 100.00
spi_device_csr_rw 1.640s 79.975us 1 1 100.00
spi_device_csr_aliasing 10.800s 3022.765us 1 1 100.00
spi_device_same_csr_outstanding 3.620s 224.388us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.090s 123.529us 1 1 100.00
spi_device_tl_intg_err 6.070s 1439.212us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 6.070s 1439.212us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 146.360s 221244.065us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*])
spi_device_mem_parity 48019754338175814733775812214547711277028918127469322761427116240973863351973 76
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 1482469 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 1482469 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[1006])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*])
spi_device_ram_cfg 19229057019796371234029187649072873968152242940115094475418734328489767010357 76
UVM_ERROR @ 4274141 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x8dc7c7 [100011011100011111000111] vs 0x0 [0])
UVM_ERROR @ 4290141 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc27de1 [110000100111110111100001] vs 0x0 [0])
UVM_ERROR @ 4318141 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x6cf096 [11011001111000010010110] vs 0x0 [0])
UVM_ERROR @ 4322141 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x231526 [1000110001010100100110] vs 0x0 [0])