Simulation Results: spi_device/2p

 
13/04/2026 19:14:24 DVSim: v1.30.1 sha: 4ae05e3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.90 %
  • code
  • 94.05 %
  • assert
  • 94.62 %
  • func
  • 60.02 %
  • line
  • 99.06 %
  • branch
  • 98.23 %
  • cond
  • 95.87 %
  • toggle
  • 87.74 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 52.090s 6720.182us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.160s 39.849us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 2.060s 139.383us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 18.640s 11218.951us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 14.070s 1243.223us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 1.530s 61.022us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 2.060s 139.383us 1 1 100.00
spi_device_csr_aliasing 14.070s 1243.223us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.790s 19.553us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.230s 299.025us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.920s 27.703us 1 1 100.00
mem_parity 1 1 100.00
spi_device_mem_parity 0.940s 85.201us 1 1 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 0.860s 46.440us 1 1 100.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.770s 118.359us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.770s 118.359us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 5.480s 1427.962us 1 1 100.00
spi_device_tpm_sts_read 0.830s 93.788us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 22.570s 12562.621us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 2.570s 261.117us 1 1 100.00
spi_device_flash_all 21.210s 4487.304us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 2.000s 814.872us 1 1 100.00
spi_device_flash_all 21.210s 4487.304us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 2.000s 814.872us 1 1 100.00
spi_device_flash_all 21.210s 4487.304us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 21.210s 4487.304us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 6.460s 2473.406us 1 1 100.00
spi_device_flash_all 21.210s 4487.304us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 6.460s 2473.406us 1 1 100.00
spi_device_flash_all 21.210s 4487.304us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 6.460s 2473.406us 1 1 100.00
spi_device_flash_all 21.210s 4487.304us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 6.460s 2473.406us 1 1 100.00
spi_device_flash_all 21.210s 4487.304us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 6.460s 2473.406us 1 1 100.00
spi_device_flash_all 21.210s 4487.304us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 3.100s 417.829us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 31.040s 20125.710us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 31.040s 20125.710us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 31.040s 20125.710us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 5.710s 1868.655us 1 1 100.00
spi_device_read_buffer_direct 5.440s 308.642us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 31.040s 20125.710us 1 1 100.00
spi_device_flash_all 21.210s 4487.304us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 21.210s 4487.304us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 21.210s 4487.304us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 3.930s 439.117us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 3.930s 439.117us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 52.090s 6720.182us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 13.000s 1106.787us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 1.200s 156.966us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.730s 12.927us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.980s 31.783us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 2.020s 104.680us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 2.020s 104.680us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.160s 39.849us 1 1 100.00
spi_device_csr_rw 2.060s 139.383us 1 1 100.00
spi_device_csr_aliasing 14.070s 1243.223us 1 1 100.00
spi_device_same_csr_outstanding 2.220s 80.960us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.160s 39.849us 1 1 100.00
spi_device_csr_rw 2.060s 139.383us 1 1 100.00
spi_device_csr_aliasing 14.070s 1243.223us 1 1 100.00
spi_device_same_csr_outstanding 2.220s 80.960us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.250s 785.425us 1 1 100.00
spi_device_tl_intg_err 5.720s 503.868us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 5.720s 503.868us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 95.000s 39433.363us 1 1 100.00