Simulation Results: sram_ctrl/main

 
13/04/2026 19:14:24 DVSim: v1.30.1 sha: 4ae05e3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.49 %
  • code
  • 96.42 %
  • assert
  • 96.19 %
  • func
  • 96.85 %
  • line
  • 99.33 %
  • branch
  • 98.37 %
  • cond
  • 94.48 %
  • toggle
  • 89.90 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 5.490s 719.219us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.780s 28.992us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.770s 14.164us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.680s 43.126us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.860s 16.060us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.430s 666.901us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.770s 14.164us 1 1 100.00
sram_ctrl_csr_aliasing 0.860s 16.060us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 126.900s 10339.778us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 66.350s 5251.375us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 265.400s 17915.712us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 173.960s 7074.288us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 1519.290s 72622.631us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 544.120s 33462.824us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 21.290s 4909.097us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 481.160s 10168.428us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 19.510s 919.415us 1 1 100.00
sram_ctrl_partial_access_b2b 304.650s 33930.437us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 6.730s 1426.912us 1 1 100.00
sram_ctrl_throughput_w_partial_write 13.950s 713.947us 1 1 100.00
sram_ctrl_throughput_w_readback 17.010s 826.371us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 223.600s 7688.602us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 3.490s 357.962us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 2150.370s 55754.506us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.790s 13.567us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.860s 1167.378us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.860s 1167.378us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.780s 28.992us 1 1 100.00
sram_ctrl_csr_rw 0.770s 14.164us 1 1 100.00
sram_ctrl_csr_aliasing 0.860s 16.060us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.960s 83.332us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.780s 28.992us 1 1 100.00
sram_ctrl_csr_rw 0.770s 14.164us 1 1 100.00
sram_ctrl_csr_aliasing 0.860s 16.060us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.960s 83.332us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 18.100s 7350.050us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 2.540s 579.482us 1 1 100.00
sram_ctrl_tl_intg_err 2.560s 211.239us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 2.540s 579.482us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.560s 211.239us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 223.600s 7688.602us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 223.600s 7688.602us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.770s 14.164us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 481.160s 10168.428us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 481.160s 10168.428us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 481.160s 10168.428us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 21.290s 4909.097us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.560s 2789.852us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 18.100s 7350.050us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 4.410s 2560.611us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 5.490s 719.219us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 5.490s 719.219us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 481.160s 10168.428us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 2.540s 579.482us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 21.290s 4909.097us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 2.540s 579.482us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 2.540s 579.482us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 5.490s 719.219us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 2.540s 579.482us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 21.890s 853.224us 1 1 100.00